Semiconductor Group
1
1998-10-01
16 MBit Synchronous DRAM
The HYB39S16400/800/160CT are dual bank Synchronous DRAM's based on SIEMENS 0.25
m
process and organized as 2 banks
2 MBit
4, 2 banks
1 MBit
8 and 2 banks
512 kbit
16 respectively. These synchronous devices achieve high speed data transfer rates up to 125
MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output
data to a system clock. The chip is fabricated with SIEMENS' advanced 16 MBit DRAM process
technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to
occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up
to 125 MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V
0.3V power supply and are available in TSOPII packages.
These Synchronous DRAM devices are available with LV-TTL interfaces.
High Performance:
Fully Synchronous to Positive Clock Edge
0 to 70
C operating temperature
Dual Banks controlled by A11 ( Bank Select)
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence:
Sequential or Interleave
Programmable Burst Length: 1, 2, 4, 8
Full page (optional) for sequencial wrap
around
-8
-10
Units
f
CK(MAX.)
125
100
MHz
t
CK3
8
10
ns
t
AC3
6
7
ns
t
CK2
10
12
ns
t
AC2
6
8
ns
Multiple Burst Read with Single Write
Operation
Automatic and Controlled Precharge
Command
Data Mask for Read/Write control
Dual Data Mask for byte control (
16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
4096 refresh cycles/64 ms
Random Column Address every CLK
(1-N Rule)
Single 3.3 V
0.3 V Power Supply
LVTTL Interface
Plastic Packages:
P-TSOPI-44 400mil width (
4,
8)
P-TSOPII-50 400mil width (
16 )
-8 version for PC100 applications
HYB 39S16400/800/160CT-8/-10
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
2
1998-10-01
Ordering Information
Type
Ordering Code
Package
Description
LVTTL-Version
HYB 39S16400CT-8
on request
P-TSOPII-44-1 400 mil
125 MHz 2B
2 M
4 SDRAM, PC100 2-2-2
HYB 39S16400CT-10
on request
P-TSOPII-44-1 400 mil
100 MHz 2B
2 M
4 SDRAM, PC66 2-2-2
HYB 39S16800CT-8
on request
P-TSOPII-44-1 400 mil
125 MHz 2B
1 M
8 SDRAM, PC100 2-2-2
HYB 39S16800CT-10
on request
P-TSOPII-44-1 400 mil
100 MHz 2B
1 M
8 SDRAM, PC66 2-2-2
HYB 39S16160CT-8
on request
P-TSOPII-50 400 mil
125 MHz 2B
512k
16 SDRAM
HYB 39S16160CT-10
on request
P-TSOPII-50 400 mil
100 MHz 2B
512k
1 SDRAM
Pin Names
CLK
Clock Input
DQ
Data Input /Output
CKE
Clock Enable
DQM, LDQM,
UDQM
Data Mask
CS
Chip Select
V
DD
Power (+ 3.3 V)
RAS
Row Address Strobe
V
SS
Ground
CAS
Column Address Strobe
V
DDQ
Power for DQ's (+ 3.3 V)
WE
Write Enable
V
SSQ
Ground for DQ's
A0 - A10
Address Inputs
NC
Not connected
A11 (BS)
Bank Select
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
3
1998-10-01
Pin Configuration
SPP03401
20
28
19
17
18
16
15
DQ0
N.C.
DQ2
DD
V
9
10
12
11
2
3
4
5
1
13
40
32
31
30
29
36
37
38
39
35
34
7
6
8
33
14
DQ3
N.C.
WE
A6
A5
A4
A3
A2
A0
22
21
CKE
A1
SS
V
42
43
44
41
CLK
DQM
N.C.
A7
A8
A9
N.C.
CAS
RAS
CS
A11
A10
26
27
N.C.
SS
V
SSQ
V
V
DDQ
V
DDQ
SSQ
V
DQ1
DDQ
V
N.C.
V
SSQ
V
DDQ
V
DD
N.C.
N.C.
SSQ
V
25
23
24
N.C.
SPP03402
20
28
19
17
18
16
15
DQ1
DQ5
DQ4
DD
V
9
10
12
11
2
3
4
5
1
13
40
32
31
30
29
36
37
38
39
35
34
7
6
8
33
14
DQ6
DQ7
WE
A6
A5
A4
A3
A2
A0
22
21
CKE
A1
SS
V
42
43
44
41
CLK
DQM
N.C.
A7
A8
A9
N.C.
CAS
RAS
CS
A11
A10
26
27
DQ0
SS
V
SSQ
V
V
DDQ
V
DDQ
SSQ
V
DQ3
DDQ
V
N.C.
V
SSQ
V
DDQ
V
DD
N.C.
DQ2
SSQ
V
25
23
24
N.C.
SPP03403
20
28
19
17
18
16
15
DQ0
DQ1
DQ2
DQ6
DQ11
DQ10
DQ9
DQ8
DD
V
9
10
12
11
2
3
4
5
1
13
40
32
31
30
29
36
37
38
39
35
34
7
6
8
33
14
DQ5
DQ4
DQ12
DQ13
DQ14
DQ15
WE
A6
A5
A4
A3
A2
A0
22
21
CKE
A1
23
24
25
SS
V
46
47
48
50
49
42
43
44
45
41
CLK
UDQM
N.C.
A7
A8
A9
N.C.
CAS
RAS
CS
A11
A10
26
27
SSQ
V
DQ3
SS
V
SSQ
V
V
DDQ
V
DDQ
SSQ
V
DQ7
DDQ
V
LDQM
V
SSQ
V
DDQ
V
DD
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
4
1998-10-01
Signal Pin Description
Pin
Type
Signal Polarity Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on
the rising edge of the clock.
CKE
Input
Level
Active
High
Activates the CLK signal when high and deactivates the CLK
signal when low, thereby inititiates either the Power Down mode,
Suspend mode or the Self Refresh mode.
CS
Input
Pulse
Active
Low
CS enables the command decoder when low and disables the
command decoder when high. When the command decoder is
disabled, new commands are ignored but previous operations
continue.
RAS
CAS
WE
Input
Pulse
Active
Low
When sampled at the positive rising edge of the clock, CAS,
RAS, and WE define the command to be executed by the
SDRAM.
A0 -
A10
Input
Level
During a Bank Activate command cycle, A0 - A10 defines the
row address (RA0 - RA10) when sampled at the rising clock
edge.
During a Read or Write command cycle, A0 - A9 defines the
column address (CA0 - CAn) when sampled at the rising clock
edge. CAn depends from the SDRAM organisation.
4M
4 SDRAM CAn = CA9
2M
8 SDRAM CAn = CA8
1M
16 SDRAM CAn = CA7
In addition to the column address, A10 is used to invoke auto-
precharge operation at the end of the burst read or write cycle. If
A10 is high, autoprecharge is selected and A11 defines the bank
to be precharged (low = bank A, high = bank B). If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction
with A11 to control which bank(s) to precharge. If A10 is high,
both bank A and bank B will be precharged regardless of the
state of A11. If A10 is low, then A11 is used to define which bank
to precharge.
A11
(BS)
Input
Level
Selects which bank is to be active. A11 low selects bank A and
A11 high selects bank B.
DQx
Input
Output
Level
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
DQM,
LDQM,
UDQM
Input
Pulse
Active
High
The Data Input/Output mask places the DQ buffers in a high
impedance state when sampled high. In Read mode, DQM has
a latency of two clock cycles and controls the output buffers like
an output enable. In Write mode, DQM has a latency of zero and
operates as a word mask by allowing input data to be written if it
is low but blocks the write operation if DQM is high.
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
5
1998-10-01
Block Diagram for HYB 39S16400CT (2 banks
2 M
4 SDRAM)
V
DD
V
SS
Supply
Power and ground for the input buffers and the core logic.
V
DDQ
V
SSQ
Supply
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
Signal Pin Description (cont'd)
Pin
Type
Signal Polarity Function
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)
Address Buffers (12)
CLK Buffer
CLK
Row
Address
Counter
CS Buffer
RAS Buffer
CAS Buffer
WE Buffer
DQM Buffer
CS
RAS
CAS
WE
DQM
Command Decoder
Self
Refresh Clock
CKE Buffer
CKE
2048 x 1024
Memory Bank A
and DQ Gate
Sense Amplifiers
Row/Column
Select
Bank A
Predecode A
Sequential
Mode Register
Control
Bank A
Control
Predecode B
Bank B
Sequential
Row/Column
Bank B
Select
Row Decoder
Data Latches
Data Latches
and DQ Gate
Row Decoder
Memory Bank B
2048 x 1024
Sense Amplifiers
Data Input/Output Buffers
2048
8
4
12
8
8
12
11
11
11
3
3
8
2048
DQ0
DQ1
DQ2
DQ3
Column Decoder
Column Decoder
SPB02835
1024
1024
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
6
1998-10-01
Block Diagram for HYB 39S16800CT (2 banks
1 M
8 SDRAM)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)
Address Buffers (12)
CLK Buffer
CLK
Row
Address
Counter
CS Buffer
RAS Buffer
CAS Buffer
WE Buffer
DQM Buffer
CS
RAS
CAS
WE
DQM
Command Decoder
Self
Refresh Clock
CKE Buffer
CKE
2048 x 512
Memory Bank A
and DQ Gate
Sense Amplifiers
Row/Column
Select
Bank A
Predecode A
Sequential
Mode Register
Control
Bank A
Control
Predecode B
Bank B
Sequential
Row/Column
Bank B
Select
Row Decoder
Data Latches
Data Latches
and DQ Gate
Memory Bank B
2048 x 512
Sense Amplifiers
Data Input/Output Buffers
2048
8
8
12
8
8
8
8
12
11
11
11
3
3
8
8
8
8
2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Column Decoder
Column Decoder
SPB02836
Row Decoder
512
512
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
7
1998-10-01
Block Diagram for HYB 39S16160CT (2 banks
512k
16 SDRAM)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)
Address Buffers (12)
CLK Buffer
CLK
Row
Address
Counter
CS Buffer
RAS Buffer
CAS Buffer
WE Buffer
DQM Buffer
DQM Buffer
CS
RAS
CAS
WE
UDQM
LDQM
Command Decoder
Self
Refresh Clock
CKE Buffer
CKE
2048 x 256
Memory Bank A
and DQ Gate
Sense Amplifiers
Row/Column
Select
Bank A
Predecode A
Sequential
Mode Register
Control
Bank A
Control
Predecode B
Bank B
Sequential
Row/Column
Bank B
Select
Row Decoder
Data Latches
Data Latches
and DQ Gate
Row Decoder
Memory Bank B
2048 x 256
Sense Amplifiers
Data Input/Output Buffers
2048
256
8
16
12
8
8
16
16
12
11
11
11
3
3
16
16
16
256
8
2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
16
Column Decoder
Column Decoder
SPB02837
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
8
1998-10-01
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the most important operation commands.
Mode Register
For application flexibility, a CAS latency, a burst length, and a burst sequence can be programmed
in the SDRAM mode register. The mode set operation must be done before any activate command
after the initial power up. Any content of the mode register can be altered by reexecuting the mode
set command. Both banks must be in precharged state and CKE must be high at least one clock
before the mode set operation. After the mode register is set, a Standby or NOP command is
required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set
operation. Address input data at this timing defines parameters to be set as shown in the following
table.
Operation
CS
RAS
CAS
WE
(L/U)DQM
Standby, Ignore RAS, CAS, WE and Address
H
X
X
X
X
Row Address Strobe and Activating a Bank
L
L
H
H
X
Column Address Strobe and Read Command
L
H
L
H
X
Column Address Strobe and Write Command
L
H
L
L
X
Precharge Command
L
L
H
L
X
Burst Stop Command
L
H
H
L
X
Self Refresh Entry
L
L
L
H
X
Mode Register Set Command
L
L
L
L
X
Write Enable/Output Enable
X
X
X
X
L
Write Inhibit/Output Disable
X
X
X
X
H
No Operation (NOP)
L
H
H
H
X
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
9
1998-10-01
Address Input for Mode Set (Mode Register Operation)
SPD03138
BS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Burst Length
BT
CAS Latency
Operation Mode
Address Bus (Ax)
Mode Register (Mx)
Operation Mode
M7
M8
M9
M10
M11
Mode
Normal
0
0
0
0
0
0
0
1
X
X
with Single
Multiple Burst
Write
0
0
0
Reserve
Latency
M6
M5
M4
CAS Latency
1
0
0
1
2
0
1
0
3
0
1
1
Reserve
1
0
0
Reserve
1
0
1
0
1
1
Reserve
Reserve
1
1
1
Sequential Burst Addressing
Interleave Burst Addressing
0
0
1
0
2
0
3
0
4
0
5
1
0
6
6
5
4
3
2
1
0
7
7
6
5
4
3
2
1
2
3
4
5
1
2
3
4
5
6
7
1
2
4
3
7
6
5
4
3
2
1
3
1
2
4
5
6
7
7
6
5
6
7
7
7
6
5
4
3
2
1
7
6
5
4
3
2
1
0
0
2
4
6
3
5
7
4
6
0
5
7
1
3
5
7
1
4
6
0
2
2
0
6
3
1
7
5
3
1
7
2
0
6
4
0
2
4
1
3
5
7
1
3
5
0
2
4
6
0
Sequential
Type
M3
Interleave
1
Burst Type
1
1
1
Full Page
Reserve
1
1
0
1
0
1
Reserve
0
0
1
Reserve
1
1
0
0
1
0
1
0
0
Burst Length
M0
M1
M2
Sequential
0
0
0
Interleave
Length
1
2
8
Reserve
Reserve
Reserve
Reserve
4
4
8
2
1
*)
*)
optional
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
10
1998-10-01
Read and Write Access Mode
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the word line are fired. A CAS cycle is triggered by setting RAS high and
CAS low at a clock timing after a necessary delay,
t
RCD
, from the RAS timing. WE is used to define
either a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 125 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page, where full
page is an optional feature in this device. Column addresses are segmented by the burst length and
serial data accesses are done within this boundary. The first column address to be accessed is
supplied at the CAS timing and the subsequent addresses are generated automatically by the
programmed burst length and its sequence. For example, in a burst length of 8 with interleave
sequence, if the first address is `2', then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5 .
Full page burst operation is only possible using the sequential burst type and page length is a
function of the I/O organisation and column addressing. Full page burst operation do not self
terminate once the burst length has been reached. In other words, unlike burst length of 2, 3 or 8,
full page burst continues until it is terminated using another command.
Similar to the page mode of conventional DRAM's, burst read or write accesses on any column
address are possible once the RAS cycle latches sense amplifiers. The maximum
t
RAS
or the refresh
interval time limits the number of random column accesses. A new burst access can be done even
before the previous burst ends. The interrupt operation at every clock cycles is supported. When the
previous burst is interrupted, the remaining addresses are overridden by the new address with the
full burst length. An interrupt which accompanies with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.
When two banks are activated sequentially, interleaved bank read or write operations are possible.
With the programmed burst length, alternate access and precharge operations on two banks can
realize fast serial data access modes among many different pages. Once two banks are activated,
column to column interleave operation can be done between two different pages.
Refresh Mode
SDRAM has two refresh modes, a CAS-before-RAS (CBR) automatic refresh and a self refresh. All
of banks must be precharged before applying any refresh mode. An on-chip address counter
increments the word and the bank addresses and no bank information is required for both refresh
modes. The chip enters the automatic refresh mode, when RAS and CAS are held low and CKE and
WE are held high at a clock timing. The mode restores word line after the refresh and no external
precharge command is necessary. A minimum
t
RC
time is required between two automatic
refreshes in a burst refresh mode. The same rule applies to any access command after the
automatic refresh operation.
The chip has an on-chip timer and the self refresh mode is available. It enters the mode when RAS,
CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the
clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation.
After the exit command, at least one
t
RC
delay is required prior to any access command.
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
11
1998-10-01
DQM Function
DQM has two functions for data I/O read write operations. During reads, when it turns to high at a
clock timing, data outputs are disabled and become high impedance after two clock delay (DQM
Data Disable Latency
t
DQZ
). It also provides a data mask function for writes. When DQM is activated,
the write operation at the next clock is prohibited (DQM Write Mask Latency
t
DQW
= zero clocks).
Suspend Mode
During normal access mode, CKE is held high and CLK is enabled. When CKE is low, it freezes the
internal clock and extends data read and write operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency
t
CSL
).
Power Down
In order to reduce standby power consumption, a power down mode is available. Bringing CKE low
enters the power down mode and all of receiver circuits are gated. All banks must be precharged
before entering this mode. One clock delay is required for mode entry and exit. The Power Down
mode does not perform any refresh operation.
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto Precharge
function is initiated. The SDRAM automatically enters the precharge operation one clock before the
last data out for CAS latency 2 amd two clocks for CAS latency 3. If CAS10 is high when a Write
Command is issued, the Write with Auto Precharge function is initiated. The SDRAM
automatically enters the precharge operation one clock delay form the last data-in for CAS latencies
of 1 and 2 and two clocks for CAS latencies of 3. This delay is referenced as
t
DPL
.
Precharge Command
If CA10 is low, the chip needs another way to precharge. In this mode, a separate precharge
command is necessary. When RAS and WE are low and CAS is high at a clock timing, it triggers the
precharge operation. Two address bits, A10 and A11, are used to define banks as shown in the
following list. The precharge command may be applied coincident with the last of burst reads for
CAS Latency = 1 and with the second to the last read data for CAS Latencies = 2 & 3. Writes require
a time
t
WR
from the last burst data to apply the precharge command.
Bank Selection by Address Bits
A10
A11
Bank A only
Low
Low
Bank B only
Low
High
Both A and B
High
Don't Care
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
12
1998-10-01
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to
terminate the burst operation prematurely. These methods include using another Read or Write
Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst
cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst
operation but leave the bank open for future Read or Write Commands to the same page of the
active bank. When interrupting a burst with another Read or Write Command care must be taken to
avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the
easiest method to use when terminating a burst operation before it has been completed. If a Burst
Stop command is issued during a burst write operation, then any residual data from the burst write
cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is
registered will be written to the memory.
Power Up Procedure
All
V
DD
and
V
DDQ
must reach the specified voltage no later than any of input signal voltages. An
initial pause of 200
sec is required after power on. All banks have to be precharged and a minimum
of 8 auto refresh cycles are required prior to the mode register set operation.
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
13
1998-10-01
Absolute Maximum Ratings
Operating temperature range ........................................................................................ 0 to + 70
C
Storage temperature range.................................................................................... 55 to + 150
C
Input/output voltage .......................................................................... 0.5 to min (
V
CC
+ 0.5, 4.6) V
Power supply voltage
V
DD
/
V
DDQ
............................................................................. 1.0 to + 4.6 V
Power Dissipation ....................................................................................................................... 1 W
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under
"
Absolute Maximum Ratings
"
may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Notes
1. All voltages are referenced to
V
SS.
2.
V
IH
may overshoot to
V
CC
+ 2.0 V for pulse width of < 4 ns with 3.3 V.
V
IL
may undershoot to
2.0 V for pulse width < 4.0 ns with 3.3 V. Pulse width measured at 50% points with amplitude
measured peak to DC reference.
Recommended Operation and Characteristics for LV-TTL Versions
T
A
= 0 to 70
C;
V
SS
= 0 V;
V
DD
,
V
DDQ
= 3.3 V
0.3 V
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
Input high voltage
V
IH
2.0
V
CC
+ 0.3
V
1, 2, 3
Input low voltage
V
IL
0.3
0.8
V
1, 2, 3
Output high voltage (
I
OUT
= 2.0 mA)
V
OH
2.4
V
3
Output low voltage (
I
OUT
= 2.0 mA)
V
OL
0.4
V
3
Input leakage current, any input
(0 V <
V
IN
<
V
DDQ
, all other inputs = 0 V)
I
I(L)
5
5
A
Output leakage current
(DQ is disabled, 0 V <
V
OUT
<
V
CC
)
I
O(L)
5
5
A
Capacitance
T
A
= 0 to 70
C;
V
DD
= 3.3 V
0.3 V,
f
= 1 MHz
Parameter
Symbol
Values
Unit
min.
max.
Input capacitance (CLK)
C
I1
2.5
4.0
pF
Input capacitance
(A0 - A12, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM,
UDQM, LDQM))
C
I2
2.5
5.0
pF
Input/Output capacitance (DQ)
C
IO
4.0
6.5
pF
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
14
1998-10-01
Notes
1. The specified values are valid when addresses are changed no more than three times during
t
RC(MIN.)
and when No Operation commands are registered on every rising clock edge during
t
RC(MIN)
.
2. The specified values are valid when data inputs (DQ's) are stable during
t
RC(MIN.)
.
Operating Currents
T
A
= 0 to 70
o
C,
V
CC
= 3.3 V
0.3 V
(Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol Test Condition
CAS
Latency
-8
-10
Unit Note
max.
max.
Operating current
I
CC1
Burst Length = 4
t
RC
t
RC(MIN.,
t
CK
t
CK(MIN.)
,
I
O
= 0 mA
2 bank interleave operation
2
3
100
115
80
90
mA
mA
1, 2
Precharge
Standby current in
power down mode
I
CC2P
CKE
V
IL(MAX.)
,
t
CK
t
CK(MIN.)
2
2
mA
I
CC2PS
CKE
V
IL(MAX.)
,
t
CK
= infinite
1
1
mA
Precharge standby
current in non-
power down mode
I
CC2N
CKE
V
IH(MIN.)
,
t
CK
t
CK(MIN.)
input signals changed once in
3 cycles
15
15
mA
CS=
High
I
CC2NS
CKE
V
IH(MIN.)
,
t
CK
= infinite,
input signals are stable
5
5
mA
Active standby
current in power
down mode
I
CC3P
CKE
V
IL(MAX).
,
t
CK
t
CK(MIN.)
3
3
mA
I
CC3PS
CKE
V
IL(MAX.)
,
t
CK
= infinite,
input signals are stable
2
2
mA
Active standby
current in non-
power down mode
I
CC3N
CKE
V
IH(MIN.)
,
t
CK
t
CK(MIN.)
,
changed once in 3 cycles
25
25
mA
CS=
High,
1
I
CC3NS
CKE
V
IH(MIN.)
,
t
CK
= infinite,
input signals are stable
15
15
mA
Burst operating
current
I
CC4
Burst Length = full page
t
RC
= infinite
t
CK
t
CK(MIN.)
,
I
O
= 0 mA
2 banks activated
2
3
60
70
50
60
mA
1, 2
Auto (CBR) refresh
current
I
CC5
t
RC
t
RC(MIN.)
2
3
60
70
50
60
mA
mA
1, 2
Self refresh
I
CC6
CKE
0.2 V
1
1
mA
1, 2
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
15
1998-10-01
AC Characteristics
1, 2, 3
T
A
= 0 to 70
C;
V
SS
= 0 V;
V
CC
= 3.3 V
0.3 V,
t
T
= 1 ns
Parameter
Symbol
Limit Values
Unit
Note
-8
-10
min.
max.
min.
max.
Clock and Clock Enable
Clock cycle time
CAS Latency = 3
CAS Latency = 2
t
CK
8
10
10
15
ns
ns
Clock frequency
CAS Latency = 3
CAS Latency = 2
t
CK
125
100
100
66
MHz
MHz
Access time from clock
CAS Latency = 3
CAS Latency = 2
t
AC
6
6
7
8
ns
ns
2, 4
Clock High Pulse width
t
CH
3
3
ns
Clock Low Pulse width
t
CL
3
3
ns
Transition time
t
T
0.5
10
0.5
10
ns
Setup and Hold Times
Input Setup time
t
IS
2
2.5
ns
5
Input Hold time
t
IH
1
1
ns
5
CKE Setup time
t
CKS
2
2.5
ns
5
CKE Hold time
t
CKH
1
1
ns
5
Mode Register Setup time
t
RSC
16
20
ns
Power Down Mode Entry time
t
SB
0
8
0
10
ns
Common Parameters
Row to Column delay time
t
RCD
20
30
ns
Row Precharge time
t
RP
20
30
ns
Row Active time
t
RAS
50
100k
60
100k
ns
Row Cycle time
t
RC
70
90
ns
Activate (a) to Activate (b) Command
period
t
RRD
16
20
ns
CAS (a) to CAS (b) Command period
t
CCD
1
1
CLK
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
16
1998-10-01
Refresh Cycle
Refresh period (4096 cycles)
t
REF
64
64
ms
Self Refresh Exit time
t
SREX
10
10
ns
Read Cycle
Data Out Hold time
t
OH
3
3
ns
2
Data Out to Low Impedance time
t
LZ
0
0
ns
Data Out to High Impedance time
t
HZ
3
8
3
10
ns
8
DQM Data Out Disable latency
t
DQZ
2
2
CLK
Write Cycle
Write Recovery time
t
WR
2
2
CLK
DQM Write Mask latency
t
DQW
0
0
CLK
Write latency
t
WL
0
0
CLK
Frequency vs. AC Parameter Relationship Table
-8-parts
CL
t
RC
t
RAS
t
RP
t
RRD
t
RCD
t
CCD
WL
t
WR
125 MHz
3
9
6
3
2
3
1
0
2
100 MHz
2
7
5
2
2
2
1
0
2
-10-parts
CL
t
RC
t
RAS
t
RP
t
RRD
t
RCD
t
CCD
WL
t
WR
100 MHz
3
8
6
3
2
3
1
0
2
83 MHz
2
6
5
2
2
2
1
0
2
AC Characteristics (cont'd)
1, 2, 3
T
A
= 0 to 70
C;
V
SS
= 0 V;
V
CC
= 3.3 V
0.3 V,
t
T
= 1 ns
Parameter
Symbol
Limit Values
Unit
Note
-8
-10
min.
max.
min.
max.
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
17
1998-10-01
Notes for AC Parameters
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests for LV-TTL versions have
V
IL
= 0.4 V and
V
IH
= 2.4 V with the timing referenced
to the 1.5 V crossover point. The transition time is measured between
V
IH
and
V
IL
. All AC
measurements assume
t
T
= 1 ns with the AC output load circuit shown in figure below. Specified
t
AC
and
t
OH
parameters are measured with a 50 pF only, without any resistive termination and
with a input signal of 1V/ s edge rate between 0.8 V and 2.0 V.
3. If clock rising time is longer than 1 ns, a time (
t
T
/2 - 0.5) ns has to be added to this parameter.
4. If tT is longer than 1 ns, a time (
t
T
-1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycle and depend on the operating frequency
of the clock, as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole
number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to
t
RC
is satisfied
once the Self Refresh Exit command is registered.
50 pF
I/O
Measurement conditions for
t
AC
and
t
OH
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
18
1998-10-01
Package Outlines
Plastic Package P-TSOPII-44
(400 mil, 0.8 mm lead pitch)
Thin Small Outline Package, SMD
GPX05941
18.41
0.13
1)
1
44
0.8
0.35
+0.1
-0.05
0.1
1
0.1
10.16
0.13
0.2
11.76
0.1
0.5
44x
0.05
0.05
0.15
-0.03
+0.06
15
5
15
5
6 max
2.5 max
2)
3)
23
22
Index Marking
Does not include dambar protrusion of 0.13 max per side
Does not include plastic protrusion of 0.25 max per side
Does not include plastic or metal protrusion of 0.15 max per side
3)
2)
1)
16.8
0.8
21x
=
0.2
M
44x
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information"
.
Dimensions in mm
SMD = Surface Mounted Device
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
19
1998-10-01
Plastic Package P-TSOPII-50
(400 mil, 0.8 mm lead pitch)
Thin Small Outline Package, SMD
GPX05956
1
25
26
50
20.95
0.131)
0.8
0.1
0.05
1.2 max.
10.16
0.13
11.76
0.2
1
0.05
0.1
0.2
50x
M
0.1
0.05
+
0.4
Index Marking
1) Does not include plastic or metal protrusion of 0.25 max. per side
0.15
+
0.06 0.03
0.1
0.5
-
-
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information"
.
Dimensions in mm
SMD = Surface Mounted Device
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