Semiconductor Group
1
4.98
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
16 MBit Synchronous DRAM
Advanced Information
The HYB39S16400/800/160BT are dual bank Synchronous DRAM's based on the die revisions "D",
& "E" and organized as 2 banks x 2MBit x4, 2 banks x 1MBit x8 and 2 banks x 512kbit x16
respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by
employing a chip architecture that prefetches multiple bits and then synchronizes the output data to
a system clock. The chip is fabricated with SIEMENS' advanced 16MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 125
MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply and are available in TSOPII packages.
These Synchronous DRAM devices are available with LV-TTL interfaces.
High Performance:
Fully Synchronous to Positive Clock Edge
0 to 70
C operating temperature
Dual Banks controlled by A11 ( Bank Select)
Programmable CAS Latency : 2, 3
Programmable Wrap Sequence : Sequential
or Interleave
Programmable Burst Length: 1, 2, 4, 8
full page(optional) for sequencial wrap
around
-8
-10
Units
fCK(max.)
125
100
MHz
tCK3
8
10
ns
tAC3
6
7
ns
tCK2
10
13.3
ns
tAC2
6
8
ns
Multiple Burst Read with Single Write
Operation
Automatic and Controlled Precharge
Command
Data Mask for Read / Write control (x4, x8)
Dual Data Mask for byte control ( x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
4096 refresh cycles / 64 ms
Random Column Address every CLK
( 1-N Rule)
Single 3.3V +/- 0.3V Power Supply
LVTTL Interface
Plastic Packages:
P-TSOPI-44 400mil width ( x4, x8 )
P-TSOPII -50 400 mil width ( x 16 )
-8 version for PC100 applications
Semiconductor Group
2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Ordering Information
Pin Description and Pinouts:
Type
Ordering Code
Package
Description
LVTTL-version:
HYB 39S16400BT-8
P-TSOPII-44 (400mil)
125MHz 2B x 2M x 4 SDRAM
HYB 39S16400BT-10
P-TSOPII-44-(400mil)
100MHz 2B x 2M x 4 SDRAM
HYB 39S16800BT-8
P-TSOPII-44-(400mil)
125MHz 2B x 1M x 8 SDRAM
HYB 39S16800BT-10
P-TSOPII-44 (400mil)
100MHz 2B x 1M x 8 SDRAM
HYB 39S16160BT-8
P-TSOPII-50 (400mil)
125MHz 2B x 512k x 16 SDRAM
HYB 39S16160BT-10
P-TSOPII-50-(400mil)
100MHz 2B x 512k x 16 SDRAM
CLK
Clock Input
DQ
Data Input /Output
CKE
Clock Enable
DQM, LDQM, UDQM
Data Mask
CS
Chip Select
Vdd
Power (+3.3V)
RAS
Row Address Strobe
Vss
Ground
CAS
Column Address Strobe
Vddq
Power for DQ's (+ 3.3V)
WE
Write Enable
Vssq
Ground for DQ's
A0-A10
Address Inputs
NC
not connected
A11 (BS)
Bank Select
Semiconductor Group
3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Vdd
NC
Vssq
DQ0
Vddq
NC
Vssq
DQ1
Vddq
NC
NC
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Vss
NC
Vssq
DQ3
Vddq
NC
Vssq
DQ2
Vddq
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
21
22
44
43
42
41
A3
Vdd
A4
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Vdd
DQ0
Vssq
DQ1
Vddq
DQ2
Vssq
DQ3
Vddq
NC
NC
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Vss
DQ7
Vssq
DQ6
Vddq
DQ5
Vssq
DQ4
Vddq
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
21
22
44
43
42
41
A3
Vdd
A4
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Vdd
DQ0
DQ1
Vssq
DQ2
DQ3
Vddq
DQ4
DQ5
Vssq
DQ6
DQ7
Vddq
LDQM
WE
CAS
RAS
CS
A11
A10
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Vss
DQ15
DQ14
Vssq
DQ13
DQ12
Vddq
DQ11
DQ10
Vssq
DQ9
DQ8
Vddq
NC
UDQM
CLK
CKE
NC
A9
A8
21
22
44
43
42
41
A0
A1
A7
A6
23
24
25
50
49
48
47
46
45
A2
A3
Vdd
A5
A4
Vss
TSOPII-44
2 Bank x 2MBit x 4
HYB39S16400BT
HYB39S16800BT
2 Bank x 1MBit x 8
TSOPII-44
( 400 mil x 725 mil)
( 400 mil x 725 mil )
HYB39S16160BT
2 Bank x 512kbit x 16
TSOPII-50
( 400 mil x 825 mil )
Semiconductor Group
4
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Signal Pin Description
Pin
Type
Signal Polarity
Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising
edge of the clock.
CKE
Input
Level
Active
High
Activates the CLK signal when high and deactivates the CLK signal when
low, thereby inititiates either the Power Down mode, Suspend mode or the
Self Refresh mode.
CS
Input
Pulse
Active
Low
CS enables the command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new
commands are ignored but previous operations continue.
RAS,
CAS
WE
Input
Pulse
Active
Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE
define the command to be executed by the SDRAM.
A0 -
A10
Input
Level
--
During a Bank Activate command cycle, A0-A10 defines the row address
(RA0-RA10) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column
address (CA0-CAn) when sampled at the rising clock edge.CAn depends
from the SDRAM organisation.
4M x 4 SDRAM CAn = CA9
2M x 8 SDRAM CAn = CA8
1M x 16 SDRAM CAn = CA7
In addition to the column address, A10 is used to invoke autoprecharge
operation at the end of the burst read or write cycle. If A10 is high,
autoprecharge is selected and A11 defines the bank to be precharged
(low=bank A, high=bank B). If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with A11
to control which bank(s) to precharge. If A10 is high, both bank A and bank
B will be precharged regardless of the state of A11. If A10 is low, then A11
is used to define which bank to precharge.
A11
(BS)
Input
Level
--
Selects which bank is to be active. A11 low selects bank A and A11 high
selects bank B.
DQx
Input
Output
Level
--
Data Input/Output pins operate in the same manner as on conventional
DRAMs.
DQM
LDQM
UDQM
Input
Pulse
Active
High
The Data Input/Output mask places the DQ buffers in a high impedance
state when sampled high. In Read mode, DQM has a latency of two clock
cycles and controls the output buffers like an output enable. In Write
mode, DQM has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the write operation if
DQM is high.
VDD,
VSS
Supply
Power and ground for the input buffers and the core logic.
VDDQ
VSSQ
Supply
--
--
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
Semiconductor Group
5
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Block Diagram for HYB39S16400BT (2 banks x 4M x 4 SDRAM)
D
a
ta
In
p
u
t
/Ou
tp
u
t
Bu
ffe
r
s
CKE Buffer
CLK Buffer
CS Buffer
RAS Buffer
CAS Buffer
WE Buffer
DQM Buffer
CKE
CLK
CS
RAS
CAS
DQM
WE
Co
mma
n
d
De
c
o
d
e
r
Mode Register
Refresh Clock
Row
Address
Counter
Self
A1
A2
A3
A4
A5
A6
A7
A10
A8
A9
A0
A11 (BS)
12
12
2048
Sequential
Control
Bank A
Row/Column
Select
Bank A
Predecode A
8
Data Latches
Column Decoder and DQ Gate
Sense Amplifiers
10
24
Memory Bank A
2048 x 1024
2048
Ro
w De
c
o
d
e
r
8
Sequential
Control
Bank B
Predecode B
8
Data Latches
Column Decoder and DQ Gate
Sense Amplifiers
102
4
Memory Bank B
2048 x 1024
2048
Ro
w De
c
o
d
e
r
8
Ad
dr
es
s
Buf
f
er
s
(
12)
Row/Column
Select
Bank B
3
11
3
11
11
4
DQ1
DQ2
DQ3
DQ0
Semiconductor Group
6
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Block Diagram for HYB39S16800BT (2 banks x 1M x 8 SDRAM)
DQ0
Data Latches
Data Latches
8
8
Column Decoder and DQ Gate
Sense Amplifiers
D
a
ta
In
p
u
t/
Ou
tp
u
t
Bu
f
f
e
r
s
8
CKE Buffer
CLK Buffer
CS Buffer
RAS Buffer
CAS Buffer
WE Buffer
DQM Buffer
CKE
CLK
CS
RAS
CAS
DQM
WE
C
o
m
m
an
d D
e
c
o
d
e
r
Mode Register
Refresh Clock
Row
Address
Counter
Self
A1
A2
A3
A4
A5
A6
A7
A10
A8
A9
A0
A11 (BS)
12
12
Sequential
Control
Bank A
Row/Column
Select
Bank A
Predecode A
Column Decoder and DQ Gate
Sense Amplifiers
Sequential
Control
Bank B
Predecode B
8
A
d
dr
es
s
B
u
f
f
e
r
s
(
1
2)
Row/Column
Select
Bank B
3
11
3
11
11
Data Latches
8
Column Decoder and DQ Gate
Sense Amplifiers
51
2
Memory Bank B
2048 x 1024
Memory Bank B
2048 x 512
2048
Ro
w De
c
o
d
e
r
Ro
w De
c
o
d
e
r
8
8
8
8
8
8
8
10
24
51
2
Memory Bank A
2048 x 512
2048
Ro
w
De
c
o
d
e
r
R
o
w De
c
o
d
e
r
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Semiconductor Group
7
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Block Diagram for HYB39S16160BT (2 banks x 512k x 16 SDRAM)
Column Decoder and DQ Gate
Sense Amplifiers
Data Latches
Data Latches
8
8
Column Decoder and DQ Gate
Sense Amplifiers
Column Decoder and DQ Gate
Sense Amplifiers
102
4
51
2
Memory Bank A
2048 x 512
Ro
w De
c
o
d
e
r
Ro
w De
c
o
d
e
r
Data Latches
Data Latches
8
8
Column Decoder and DQ Gate
Sense Amplifiers
8
CKE Buffer
CLK Buffer
CS Buffer
RAS Buffer
CAS Buffer
WE Buffer
DQM Buffer
CKE
CLK
CS
RAS
CAS
UDQM
WE
C
o
m
m
an
d D
e
c
o
de
r
Mode Register
Refresh Clock
Row
Address
Counter
Self
A1
A2
A3
A4
A5
A6
A7
A10
A8
A9
A0
A11 (BS)
12
12
Sequential
Control
Bank A
Row/Column
Select
Bank A
Predecode A
Column Decoder and DQ Gate
Sense Amplifiers
Sequential
Control
Bank B
Predecode B
8
Ad
dr
es
s
B
u
f
f
e
r
s
(
1
2)
Row/Column
Select
Bank B
3
11
3
11
11
16
16
16
16
16
16
10
24
25
6
Memory Bank A
2048 x 256
2048
Ro
w De
c
o
d
e
r
Ro
w De
c
o
d
e
r
Data Latches
Data Latches
8
Column Decoder and DQ Gate
Sense Amplifiers
25
6
Memory Bank B
2048 x 1024
Memory Bank B
2048 x 512
Memory Bank B
2048 x 1024
Memory Bank B
2048 x 256
2048
R
o
w De
c
o
d
e
r
Ro
w De
c
o
d
e
r
Ro
w De
c
o
d
e
r
R
o
w De
c
o
d
e
r
D
a
ta
In
p
u
t/Ou
tp
u
t
Bu
ffe
r
s
DQM Buffer
LDQM
16
DQ1
DQ2
DQ3
DQ4
DQ5
DQ0
DQ6
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ8
DQ14
DQ15
Semiconductor Group
8
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the most important operation commands.
Mode Register
For application flexibility, a CAS latency, a burst length, and a burst sequence can be
programmed in the SDRAM mode register. The mode set operation must be done before any
activate command after the initial power up. Any content of the mode register can be altered by re-
executing the mode set command. Both banks must be in precharged state and CKE must be high
at least one clock before the mode set operation. After the mode register is set, a Standby or NOP
command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate
the mode set operation. Address input data at this timing defines parameters to be set as shown in
the following table.
Operation
CS
RAS
CAS
WE
(L/U)DQM
Standby, Ignore RAS, CAS, WE and Address
H
X
X
X
X
Row Address Strobe and Activating a Bank
L
L
H
H
X
Column Address Strobe and Read Command
L
H
L
H
X
Column Address Strobe and Write Command
L
H
L
L
X
Precharge Command
L
L
H
L
X
Burst Stop Command
L
H
H
L
X
Self Refresh Entry
L
L
L
H
X
Mode Register Set Command
L
L
L
L
X
Write Enable/Output Enable
X
X
X
X
L
Write Inhibit/Output Disable
X
X
X
X
H
No Operation (NOP)
L
H
H
H
X
Semiconductor Group
9
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Address Input for Mode Set (Mode Register Operation)
Sequential Burst Addressing
Interleave Burst Addressing
0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0
2 3 4 5 6 7 0 1
3 4 5 6 7 0 1 2
4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4
6 7 0 1 2 3 4 5
7 0 1 2 3 4 5 6
0 1 2 3 4 5 6 7
1 0 3 2 5 4 7 6
2 3 0 1 6 7 4 5
3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
7 6 5 4 3 2 1 0
BS
A3
A4
A2
A1
A0
A10 A9
A8
A7
A6
A5
Address Bus (Ax)
BT
Burst Length
CAS Latency
Mode Register (Mx)
CAS Latency
M6
M5
M4
Latency
0
0
0
Reserve
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
Reserve
1
0
1
Reserve
1
1
0
Reserve
1
1
1
Reserve
Burst Length
M2
M1
M0
Length
Sequential
Interleave
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserve
Reserve
1
0
1
Reserve
Reserve
1
1
0
Reserve
Reserve
1
1
1
Full Page*)
Reserve
Burst
Type
M3
Type
0
Sequential
1
Interleave
Operation Mode
M11 M10 M9 M8 M7
Mode
0
0
0
0
0
Normal
X
X
1
0
0
Multiple Burst
with Single
Write
Operation Mode
*) optional
Semiconductor Group
10
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Read and Write Access Mode
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the word line are fired. A CAS cycle is triggered by setting RAS high and
CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define
either a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read
or write operations are allowed at up to a 125 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page, where full
page is an optional feature in this device. Column addresses are segmented by the burst length and
serial data accesses are done within this boundary. The first column address to be accessed is
supplied at the CAS timing and the subsequent addresses are generated automatically by the
programmed burst length and its sequence. For example, in a burst length of 8 with interleave
sequence, if the first address is `2', then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5 .
Full page burst operation is only possible using the sequential burst type and page length is
a function of the I/O organisation and column addressing. Full page burst operation do not self
terminate once the burst length has been reached. In other words, unlike burst length of 2, 3 or 8,
full page burst continues until it is terminated using another command.
Similar to the page mode of conventional DRAM's, burst read or write accesses on any column
address are possible once the RAS cycle latches sense amplifiers. The maximum tRAS or the
refresh interval time limits the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycles is
supported. When the previous burst is interrupted, the remaining addresses are overridden by the
new address with the full burst length. An interrupt which accompanies with an operation change
from a read to a write is possible by exploiting DQM to avoid bus contention.
When two banks are activated sequentially, interleaved bank read or write operations are
possible. With the programmed burst length, alternate access and precharge operations on two
banks can realize fast serial data access modes among many different pages. Once two banks are
activated, column to column interleave operation can be done between two different pages.
Refresh Mode
SDRAM has two refresh modes, a CAS before RAS (CBR) automatic refresh and a self refresh.
All of banks must be precharged before applying any refresh mode. An on-chip address counter
increments the word and the bank addresses and no bank information is required for both refresh
modes. The chip enters the automatic refresh mode, when RAS and CAS are held low and CKE and
WE are held high at a clock timing. The mode restores word line after the refresh and no external
precharge command is necessary. A minimum tRC time is required between two automatic
refreshes in a burst refresh mode. The same rule applies to any access command after the
automatic refresh operation.
The chip has an on-chip timer and the self refresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals
including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh
exit operation. After the exit command, at least one tRC delay is required prior to any access
command.
Semiconductor Group
11
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
DQM Function
DQM has two functions for data I/O read write operations. During reads, when it turns to high
at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM
Data Disable Latency t
DQZ
). It also provides a data mask function for writes. When DQM is
activated, the write operation at the next clock is prohibited (DQM Write Mask Latency t
DQW
= zero
clocks).
Suspend Mode
During normal access mode, CKE is held high and CLK is enabled. When CKE is low, it freezes
the internal clock and extends data read and write operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency t
CSL
).
Power Down
In order to reduce standby power consumption, a power down mode is available. Bringing CKE
low enters the power down mode and all of receiver circuits are gated. All banks must be
precharged before entering this mode. One clock delay is required for mode entry and exit. The
Power Down mode does not perform any refresh operation.
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge
function is initiated. The SDRAM automatically enters the precharge operation one clock after the
Read Command is registered for CAS latencies of 1 and 2, and two clocks for CAS latencies of 3.
If CAS10 is high when a Write Command is issued, the Write with Auto-Precharge function is
initiated. The SDRAM automatically enters the precharge operation one clock delay form the last
data-in for CAS latencies of 1 and 2 and two clocks for CAS latencies of 3. This delay is referenced
as t
DPL
.
Precharge Command
If CA10 is low, the chip needs another way to precharge. In this mode, a separate precharge
command is necessary. When RAS and WE are low and CAS is high at a clock timing, it triggers the
precharge operation. Two address bits, A10 and A11, are used to define banks as shown in the
following list. The precharge command may be applied coincident with the last of burst reads for
CAS Latency = 1 and with the second to the last read data for CAS Latencies = 2 & 3. Writes require
a time t
DPL
from the last burst data to apply the precharge command.
Bank Selection by Address Bits
A10 A11
Bank A Only Low Low
Bank B Only Low High
Both A and B High Don't Care
Semiconductor Group
12
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to
terminate the burst operation prematurely. These methods include using another Read or Write
Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst
cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst
operation but leave the bank open for future Read or Write Commands to the same page of the
active bank. When interrupting a burst with another Read or Write Command care must be taken to
avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the
easiest method to use when terminating a burst operation before it has been completed. If a Burst
Stop command is issued during a burst write operation, then any residual data from the burst write
cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is
registered will be written to the memory.
Power Up Procedure
All Vdd and Vddq must reach the specified voltage no later than any of input signal voltages. An
initial pause of 200
sec is required after power on. All banks have to be precharged and a minimum
of 2 auto-refresh cycles are required prior to the mode register set operation.
Semiconductor Group
13
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Absolute Maximum Ratings
Operating temperature range ......................................................................................... 0 to + 70
C
Storage temperature range...................................................................................... 55 to + 150
C
Input/output voltage .............................................................................. 0.5 to min(Vcc+0.5, 4.6) V
Power supply voltage VDD / VDDQ .......................................................................... 1.0 to + 4.6 V
Power Dissipation............................................. ................................................................ ..........1 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Recommended Operation and Characteristics for LV-TTL versions:
T
A
= 0 to 70
C;
V
SS
= 0 V;
V
DD,
V
DDQ
= 3.3 V
0.3 V
Notes:
1. All voltages are referenced to VSS.
2. Vih may overshoot to Vcc + 2.0 V for pulse width of < 4ns with 3.3V. Vil may undershoot to
-2.0 V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak
to DC reference.
Capacitance
T
A
= 0 to 70
C;
V
DD
= 3.3 V
0.3 V,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
Input high voltage
V
I
H
2.0
Vcc+0.3
V
1, 2, 3
Input low voltage
V
I
L
0.3
0.8
V
1, 2, 3
Output high voltage (
I
OUT
= 2.0 mA)
V
OH
2.4
V
3
Output low voltage (
I
OUT
= 2.0 mA)
V
OL
0.4
V
3
Input leakage current, any input
(0 V <
V
I
N
< Vddq, all other inputs = 0 V)
I
I
(L)
10
10
A
Output leakage current
(DQ is disabled, 0 V <
V
OUT
<
V
CC
)
I
O(L)
10
10
A
Parameter
Symbol
Values
Unit
min.
max.
Input capacitance
(CLK)
C
I
1
2.5
4.0
pF
Input capacitance
(A0-A12, BA0,BA1,RAS, CAS, WE, CS, CKE, DQM)
C
I
2
2.5
5.0
pF
Input / Output capacitance
(DQ)
C
I
O
4.0
6.5
pF
Semiconductor Group
14
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Operating Currents (T
A
= 0 to 70
o
C, VCC = 3.3V
0.3V
(Recommended Operating Conditions unless otherwise noted)
Notes:
1. The specified values are valid when addresses are changed no more than three times during trc(min.) and
when No Operation commands are registered on every rising clock edge during tRC(min).
2. The specified values are valid when data inputs (DQ's) are stable during tRC(min.).
Parameter
Symbol
Test Condition
CAS
Latency
-8
-10
Note
max. max.
Operating Current
Icc1
Burst Length = 4
trc>=trc (min.)
tck>=tck(min.), Io = 0mA
2 bank interleave operation
1
2
3
80
115
125
65
90
100
mA
mA
mA
1, 2
Precharge
Standby Current
in Power Down
Mode
Icc2P
CKE<=VIL(max),
tck>=tck(min.)
3
3
mA
Icc2PS
CKE<=VIL(max),
tCK=infinite
2
2
mA
Precharge
Standby Current
in Non-power
down Mode
Icc2N
CKE>=VIH(min),
tck>=tck(min.) input signals
changed once in 3 cycles
20
20
mA
CS=
High
Icc2NS
CKE>=VIH(min),
tCK=infinite, input signals
are stable
10
10
mA
Active Standby
Current in Power
Down Mode
Icc3P
CKE<=VIL(max),
tck>=tck(min.)
3
3
mA
Icc3PS
CKE<=VIL(max),
tCK=infinite, inpit signals
are stable
2
2
mA
Active Standby
Current in Non-
power Down
Mode
Icc3N
CKE>=VIH(min),
tck>=tck(min.),
changed once in 3 cycles
25
25
mA
CS=
High,
1
Icc3NS
CKE>=VIH(min),
tCK=infinite, input signals
are stable
15
15
mA
Burst Operating
Current
Icc4
Burst Length = full page
trc = infinite
tck >= tck (min.), IO = 0 mA
2 banks activated
1
2
3
50
80
120
40
65
95
mA
1, 2
Auto (CBR)
Refresh Current
Icc5
trc>=trc(min)
1
2
3
75
95
115
60
75
90
mA
mA
mA
1, 2
Self Refresh
Icc6
CKE=<0,2V
1
1
mA
1, 2
1
Semiconductor Group
15
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
AC Characteristics 1)2)3)
T
A
= 0 to 70
C;
V
SS
= 0 V;
V
CC
= 3.3 V
0.3 V,
t
T
= 1 ns
Parameter
Symbol
Limit Values
Unit
-8
-10
min
max
min
max
Clock and Clock Enable
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
t
CK
8
10
10
12
s
ns
ns
Clock Frequency
CAS Latency = 3
CAS Latency = 2
t
CK
125
100
100
75
MHz
MHz
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
t
AC
6
6
7
8
ns
ns
2, 4
Clock High Pulse Width
t
CH
3
3
ns
Clock Low Pulse Width
t
CL
3
3
ns
Transition time
t
T
0.5
10
0.5
10
ns
Setup and Hold Times
Input Setup Time
t
IS
2
3
ns
5
Input Hold Time
t
IH
1
1
ns
5
CKE Setup Time
t
CKS
2
3
ns
5
CKE Hold Time
t
CKH
1
1
ns
5
Mode Register Set-up time
t
RSC
16
20
ns
Power Down Mode Entry Time
t
SB
0
8
0
10
ns
Common Parameters
Row to Column Delay Time
t
RCD
20
24
ns
6
Row Active Time
t
RAS
45
100k
60
100k
ns
6
Row to Column Delay Time
t
RCD
20
24
ns
6
Row Precharge Time
t
RP
20
24
ns
6
Row Cycle Time
t
RC
70
90
ns
6
Activate(a) to Activate(b) Command
period
t
RRD
16
20
ns
6
Semiconductor Group
16
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Frequency vs. AC Parameter Relationship Table:
-8 -parts
-10 -parts:
CAS(a) to CAS(b) Command period
t
CCD
1
1
CLK
Refresh Cycle
Refresh Period
(4096 cycles)
t
REF
64
64
ms
Self Refresh Exit Time
t
SREX
10
10
ns
Read Cycle
Data Out Hold Time
t
OH
3
3
ns
2
Data Out to Low Impedance Time
t
LZ
0
0
ns
Data Out to High Impedance Time
t
HZ
3
8
3
10
ns
8
DQM Data Out Disable Latency
t
DQZ
2
2
CLK
Write Cycle
Write Recovery Time
t
WR
8
10
ns
DQM Write Mask Latency
t
DQW
0
0
CLK
Write Latency
t
WL
0
0
CLK
CL
tRC
tRAS
tRP
tRRD
tRCD
tCCD
t
WL
tWR
125 MHz
3
9
6
3
2
3
1
0
1
100 MHz
2
7
5
2
2
2
1
0
1
CL
tRC
tRAS
tRP
tRRD
tRCD
tCCD
WL
tWR
100 MHz
3
8
6
3
2
3
1
0
1
75 MHz
2
7
5
2
2
2
1
0
1
Parameter
Symbol
Limit Values
Unit
-8
-10
min
max
min
max
Semiconductor Group
17
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests for LV-TTL versions have V
il
= 0.4 V and V
ih
= 2.4 V with the timing referenced to the 1.4 V
crossover point. The transition time is measured between V
ih
and V
il
. All AC measurements assume t
T
=1ns
with the AC output load circuit shown in fig.1. Specified tac and toh parameters are measured with a 50 pF only,
without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V.
3. If clock rising time is longer than 1 ns, a time (t
T
/2 - 0.5) ns has to be added to this parameter.
4. If tT is longer than 1 ns, a time (t
T
-1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock,
as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit
command is registered.
1.4V
1.4V
tSETUP
tHOLD
tAC
tAC
tLZ
tOH
tHZ
CLOCK
INPUT
OUTPUT
50 pF
I/O
Z=50 Ohm
+ 1.4 V
50 Ohm
2.4 V
0.4 V
t
T
fig.1
tCH
tCL
50 pF
I/O
Measurement conditions for
tac and toh
Semiconductor Group
18
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Package Outlines:
TSOP-44 (400).WMF
GLX05862
Plastic Package P-TSOPII-44
( 400mil, 0.8mm lead pitch)
Thin small outline package, SMD
Plastic Package P-TSOPII-50
( 400mil, 0.8mm lead pitch)
1) Does not include plastic or metal protusion of 0.25 max. per side
Index marking
50
26
1
25
20.95
-
+0.13
1)
0.5
11.76
10.16
+0.13
-
+0.1
-
-
+0.2
0.15
+0.06 -0.03
0.8
0.4
-0.1
+0.05
0.2
50x
0.1
M
1.2 ma
x
0.1
+0.05
-
1
+0.05
-
Thin small outline package, SMD
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
19
Timing Diagrams
1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4.2 Minimum Read to Write Interval
4.3 Non-Minimum Read to Write Interval
5. Burst Write Operation
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by Read
7. Burst Read & Write with Auto-Precharge
7.1 Burst Write with Auto Precharge
7.2 Burst Read with Auto Precharge
8. Burst Termination
8.1 Termination of a Burst Read Operation
8.2 Termination of a Burst Write Operation
9. AC- Parameters
9.1 AC Parameters for a Write Timing
9.2 AC Parameters for a Read Timing
10. Mode Register Set
11. Power on Sequence and Auto Refresh (CBR)
12. Clock Suspension (using CKE)
12.1 Clock Suspension During Burst Read CAS Latency = 1
12. 2 Clock Suspension During Burst Read CAS Latency = 2
12. 3 Clock Suspension During Burst Read CAS Latency = 3
12. 4 Clock Suspension During Burst Write CAS Latency = 1
12. 5 Clock Suspension During Burst Write CAS Latency = 2
12. 6 Clock Suspension During Burst Write CAS Latency = 3
13. Power Down Mode and Clock Suspend
14. Auto Refresh (CBR)
15. Self Refresh ( Entry and Exit)
16. Random Column Read ( Page within same Bank)
16.1 CAS Latency = 1
16.2 CAS Latency = 2
16.3 CAS Latency = 3
17. Random Column Write ( Page within same Bank)
17.1 CAS Latency = 1
17.2 CAS Latency = 2
17.3 CAS Latency = 3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
20
Timing Diagrams
(cont'd)
18. Random Row Read ( Interleaving Banks)
18.1 CAS Latency = 1
18.2 CAS Latency = 2
18.3 CAS Latency = 3
19. Random Row Write ( Interleaving Banks)
19.1 CAS Latency = 1
19.2 CAS Latency = 2
19.3 CAS Latency = 3
20. Full Page Read Cycle (optional feature)
20.1 CAS Latency = 1
20.2 CAS Latency = 2
20.3 CAS Latency = 3
21. Full Page Write Cycle (optional feature)
21.1 CAS Latency = 1
21.2 CAS Latency = 2
21.3 CAS Latency = 3
22. Precharge Termination of a Burst
22.1 CAS Latency = 1
22.2 CAS Latency = 2
22.3 CAS Latency = 3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
21
1. Bank Activate Command Cycle
(CAS latency = 3)
2. Burst Read Operation
(Burst Length = 4, CAS latency = 1, 2, 3)
ADDRESS
CLK
T0
T
T1
T
T
T
T
COMMAND
NOP
NOP
NOP
Bank A
Row Addr.
Bank A
Activate
Write A
with Auto
Bank A
Col. Addr.
. . . . . . . . . .
. . . . . . . . . .
. . . . . . . . . .
Bank B
Activate
Bank A
Row Addr.
Bank A
Activate
t
RCD
: "H" or "L"
t
RC
Precharge
t
RRD
Bank B
Row Addr.
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A0
CAS latency = 1
t
CK2,
DQ's
CAS latency = 2
t
CK3,
DQ's
CAS latency = 3
DOUT A1
DOUT A2
DOUT A3
NOP
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
t
CK1,
DQ's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
22
3. Read Interrupted by a Read
(Burst Length = 4, CAS latency = 1, 2, 3)
4.1 Read to Write Interval
(Burst Length = 4, CAS latency = 3)
COMMAND
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
t
CK1,
DQ's
CAS latency = 1
t
CK2,
DQ's
CAS latency = 2
t
CK3,
DQ's
CAS latency = 3
NOP
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
DQM
DOUT A0
DIN B0
DIN B1
DIN B2
: "H" or "L"
Must be Hi-Z before
the Write Command
DQ's
Minimum delay between the Read and Write Commands = 4+1 = 5 cycles
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
t
DQZ
t
DQW
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
23
4 2. Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 1, 2)
4. 3. Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 3
COMMAND
NOP
BANK A
NOP
READ A
WRITE A
NOP
NOP
NOP
DQM
DIN A0
DIN A1
DIN A2
DIN A3
: "H" or "L"
DIN A0
DIN A1
DIN A2
DIN A3
Must be Hi-Z before
the Write Command
t
CK1,
DQ's
CAS latency = 1
t
CK2,
DQ's
CAS latency = 2
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
ACTIVATE
1 Clk Interval
t
DQZ
t
DQW
NOP
READ A
NOP
NOP
READ A
NOP
WRITE B
NOP
NOP
DQM
DIN B0
DIN B1
DIN B2
: "H" or "L"
t
CK1,
DQ's
CAS latency = 1
t
CK2,
DQ's
CAS latency = 2
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
DOUT A1
DOUT A0
DOUT A0
DIN B0
DIN B1
DIN B2
COMMAND
DIN B0
DIN B1
DIN B2
DOUT A2
DOUT A1
DOUT A0
Must be Hi-Z before
the Write Command
t
CK3,
DQ's
CAS latency = 3
t
DQZ
t
DQW
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
24
5. Burst Write Operation
(Burst Length = 4, CAS latency = 1, 2, or 3)
6.1 Write Interrupted by a Write
(Burst Length = 4, CAS latency = 1, 2, or 3)
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
DQ's
DIN A0
DIN A1
DIN A2
DIN A3
NOP
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Extra data is ignored after
The first data element and the Write
are registered on the same clock edge.
don't care
termination of a Burst.
COMMAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
DQ's
DIN A0
DIN B0
DIN B1
DIN B2
NOP
DIN B3
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
1 Clk Interval
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
25
6.2 Write Interrupted by a Read
(Burst Length = 4, CAS latency = 1, 2, 3)
7.1
Burst Write with Auto-Precharge
Burst Length = 2, CAS latency = 1, 2, 3)
COMMAND
NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
t
CK1,
DQ's
CAS latency = 1
DIN A0
t
CK2,
DQ's
CAS latency = 2
DIN A0
t
CK3,
DQ's
CAS latency = 3
DIN A0
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Input data for the Write is ignored.
Input data must be removed from the DQ's at least one clock
cycle before the Read dataAPpears on the outputs to avoid
data contention.
don't care
don't care
don't care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
DOUT B3
COMMAND
NOP
NOP
NOP
WRITE A
Auto-Precharge
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
BANK A
ACTIVE
NOP
NOP
DIN A0
DIN A1
DIN A0
DIN A1
*
*
DQ's
CAS latency = 2
DQ's
CAS latency = 3
Begin Autoprecharge
Bank can be reactivated after trp
*
t
DPL
t
DPL
t
RP
t
RP
DIN A0
DIN A1
t
DPL
t
RP
NOP
*
DQ's
CAS latency = 1
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
26
7.2 Burst Read with Auto-Precharge
(Burst Length = 4, CAS latency = 1, 2, 3)
8.1 Termination of a Burst Read Operation
(CAS latency = 1, 2, 3 / Burst Length = 8)
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A0
CAS latency = 1
t
CK2,
DQ's
CAS latency = 2
t
CK3,
DQ's
CAS latency = 3
DOUT A1
DOUT A2
DOUT A3
NOP
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
t
CK1,
DQ's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
with AP
Begin Autoprecharge
Bank can be reactivated after trp
*
*
*
*
t
RP
t
RP
t
RP
COMMAND
READ A
NOP
NOP
NOP
Burst
NOP
NOP
NOP
NOP
t
CK1,
DQ's
CAS latency = 1
t
CK2,
DQ's
CAS latency = 2
t
CK3,
DQ's
CAS latency = 3
Stop
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
The burst ends after a delay equal to the
CAS latency.
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
27
8.2 Termination of a Burst Write Operation
(CAS Laency = 1, 2, 3, Burst Length = 8)
COMMAND
NOP
WRITE A
NOP
NOP
Burst
NOP
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
Stop
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Input data for the Write is masked.
DQ's
CAS latency = 1,2,3
don't care
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
28
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
9
.
1
A
C
Pa
ra
m
e
te
rs
for
W
r
i
t
e
T
i
mi
n
g
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bur
s
t
Leng
t
h
= 4,
CAS
Lat
ency = 2
A
d
d
r
t
CK
S
t
CS
t
CH
t
CK
H
t
AS
t
RCD
t
RC
t
RP
t
DS
A
c
ti
v
a
te
C
o
m
m
and
B
ank
A
Wr
i
t
e
w
i
t
h
Au
t
o
Pr
e
c
h
a
r
g
e
C
o
mma
nd
Ba
n
k
A
Ac
t
i
v
a
t
e
C
o
m
m
and
B
ank
B
Wr
it
e
w
i
t
h
Au
t
o
Pr
e
c
h
a
r
g
e
C
o
mman
d
B
ank
B
A
c
ti
v
a
te
C
o
mm
and
B
ank
A
Wr
it
e
C
o
m
m
and
B
ank
A
P
r
ec
har
ge
C
o
mm
and
B
ank
A
A
c
ti
v
a
te
C
o
mman
d
B
ank
A
t
DH
Ax
0
Ax
3
Ax
2
Ax
1
Bx
0
Bx
3
Bx
2
Bx
1
Ay
0
Ay
3
Ay
2
Ay
1
t
CK
2
t
CH
t
CL
B
egi
n A
u
to
P
r
ec
har
ge
B
ank
A
B
egi
n A
u
to P
r
e
c
har
ge
B
ank
B
t
DP
L
t
RRD
Ac
t
i
v
a
t
e
C
o
mm
and
Ba
n
k
B
RA
y
CB
x
R
A
y
RA
y
RB
x
RB
x
CA
x
RB
y
RB
y
RA
z
RA
z
RA
x
RA
x
t
AH
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
29
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
9
.
2
A
C
Pa
ra
m
e
te
rs
for
R
e
a
d
Ti
mi
n
g
T2
T3
T
4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T1
0
Hi
-
Z
AP
Bur
s
t
Leng
t
h
= 2,
CAS
Lat
ency = 2
A
d
d
r
t
CS
t
CH
t
CK
H
t
AS
t
AH
t
RR
D
t
RCD
t
RA
S
t
LZ
A
c
ti
v
a
te
C
o
mmand
B
ank
A
A
c
ti
v
a
te
C
o
m
m
and
B
ank
B
A
c
ti
v
a
te
C
o
m
m
and
B
ank
A
P
r
ec
har
ge
C
o
mm
and
B
ank
A
t
CK
S
t
CK
2
Ax
0
Ax
1
R
ead
C
o
mman
d
Ba
n
k
A
R
ead w
i
th
A
u
to P
r
e
c
har
ge
C
o
mmand
B
ank
B
t
RC
t
RP
t
AC
2
t
AC
2
t
OH
t
HZ
t
CH
t
CL
Bx
0
B
egi
n A
u
t
o
Pr
e
c
h
a
r
g
e
B
ank
B
Bx
1
t
HZ
RB
x
R
A
y
RB
x
RB
x
RA
y
CA
x
RA
x
RA
x
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
30
\
CLK
CKE
CS
RAS
CAS
WE
B
A
10.
Mo
de R
e
g
i
st
er
S
e
t
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
AP
A
d
d
r
Pr
e
c
h
a
r
g
e
C
o
m
m
and
A
l
l
B
ank
s
Mo
de R
egi
s
t
er
S
e
t C
o
mman
d
An
y
C
o
m
m
and
A
ddr
es
s
K
e
y
2 Cl
ock m
i
n.
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
31
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
1
1
.
P
o
we
r
o
n
Se
q
u
e
n
c
e
a
n
d
Au
t
o
Re
f
r
e
s
h
(
CBR)
TT
T
T0
TT
T
TT
T
T
T
TT
T1
TT
T
T
TT
TT
Hi
-
Z
AP
A
d
d
r
Pr
e
c
h
a
r
g
e
C
o
m
m
and
A
l
l
B
ank
s
t
RP
M
i
ni
m
u
m
of
2 Ref
r
es
h
Cy
cl
es ar
e r
equi
r
e
d
1s
t A
u
to Ref
r
es
h
C
o
mma
nd
t
RC
Hi
gh l
e
v
e
l
i
s
r
equ
i
r
ed
2nd
A
u
to
Refr
es
h
C
o
m
m
and
I
nput
s m
u
st
be
st
abl
e f
o
r
200
s
An
y
C
o
m
m
and
2
Cl
ock
m
i
n.
Mo
de R
egi
s
t
er
A
ddr
es
s
K
e
y
S
e
t C
o
mma
nd
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
32
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
12.
1 C
l
oc
k S
u
sp
ens
i
on
D
u
r
i
ng
B
u
r
s
t R
e
ad (
U
sing
C
K
E
) (1
of
3)
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bur
s
t
Leng
t
h
= 4,
CAS
Lat
ency = 1
A
d
d
r
CA
x
RA
x
Ax
0
Ax
1
Ax
2
Ax
3
A
c
ti
v
a
te
C
o
mmand
B
ank
A
R
ead
C
o
m
m
and
B
a
n
k
A
C
l
oc
k
S
u
s
pend
2 C
y
c
l
es
C
l
oc
k
S
u
s
pend
1 C
y
c
l
e
C
l
oc
k
S
u
s
pend
3 C
y
c
l
es
RA
x
t
HZ
t
CK
1
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
33
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
12.
2 C
l
oc
k S
u
sp
ens
i
on
D
u
r
i
ng
B
u
r
s
t R
e
ad (
U
sing
C
K
E
) (2
of
3)
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bur
s
t
Leng
t
h
= 4,
CAS
Lat
ency = 2
A
d
d
r
CA
x
RA
x
Ax
0
Ax
1
Ax
2
Ax
3
A
c
ti
v
a
te
C
o
mman
d
Ba
n
k
A
Cl
o
c
k
S
u
s
p
e
n
d
2 C
y
c
l
e
s
Cl
o
c
k
S
u
s
p
e
n
d
1 C
y
c
l
e
C
l
oc
k
S
u
s
p
end
3 C
y
c
l
es
RA
x
Re
a
d
C
o
mm
and
B
ank
A
t
HZ
t
CK
2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
34
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
12.
3 C
l
oc
k S
u
sp
ens
i
on
D
u
r
i
ng
B
u
r
s
t R
e
ad (
U
sing
C
K
E
) (3
of
3)
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bur
s
t
Leng
t
h
= 4,
CAS
Lat
ency = 3
A
d
d
r
RA
x
Ax
0
Ax
1
Ax
2
Ax
3
A
c
ti
v
a
te
C
o
mman
d
Ba
n
k
A
Cl
o
c
k
S
u
s
p
e
n
d
2 C
y
c
l
es
Cl
o
c
k
S
u
s
p
e
n
d
1 C
y
c
l
e
Cl
o
c
k
S
u
s
p
e
n
d
3 C
y
c
l
e
s
RA
x
R
ead
C
o
mma
nd
Ba
n
k
A
CA
x
t
HZ
t
CK
3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
35
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
12.
4 C
l
oc
k S
u
sp
ens
i
on
D
u
r
i
ng
B
u
r
s
t W
r
ite
(U
sin
g
C
K
E
) (
1
of
3)
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bur
s
t
Leng
t
h
= 4,
CAS
Lat
ency = 1
A
d
d
r
CA
x
RA
x
A
c
ti
v
a
te
C
o
mmand
B
ank
A
Wr
it
e
C
o
m
m
and
B
a
n
k
A
C
l
oc
k
S
u
s
p
end
1 C
y
c
l
e
C
l
o
c
k S
u
sp
e
n
d
2 C
y
c
l
es
C
l
oc
k
S
u
s
pend
3 C
y
c
l
es
DA
x
3
DA
x
2
DA
x
0
DA
x
1
RA
x
t
CK
1
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
36
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
12.
5 C
l
oc
k S
u
sp
ens
i
on
D
u
r
i
ng
B
u
r
s
t W
r
ite
(U
sin
g
C
K
E
) (
2
of
3)
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bur
s
t
Leng
t
h
= 4,
CAS
Lat
ency = 2
A
d
d
r
CA
x
RA
x
A
c
ti
v
a
te
C
o
mman
d
Ba
n
k
A
RA
x
DA
x
0
C
l
oc
k
S
u
s
p
end
1 C
y
c
l
e
DA
x
1
DA
x
2
DA
x
3
Cl
o
c
k
S
u
s
p
e
n
d
2 C
y
c
l
es
C
l
oc
k
S
u
s
pend
3 C
y
c
l
es
Wr
it
e
C
o
mman
d
B
ank
A
t
CK
2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
37
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
12.
6 C
l
oc
k S
u
sp
ens
i
on
D
u
r
i
ng
B
u
r
s
t W
r
ite
(U
sin
g
C
K
E
) (
3
of
3)
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bur
s
t
Leng
t
h
= 4,
CAS
Lat
ency = 3
A
d
d
r
RA
x
A
c
ti
v
a
te
C
o
mman
d
Ba
n
k
A
RA
x
CA
x
DA
x
0
C
l
oc
k
S
u
s
pend
1 C
y
c
l
e
DA
x
1
DA
x
2
DA
x
3
C
l
oc
k
S
u
s
p
end
2 C
y
c
l
es
C
l
o
c
k
S
u
s
pend
3 C
y
c
l
es
Wr
i
t
e
C
o
mma
nd
Ba
n
k
A
t
CK
3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
38
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
13.
P
o
wer
D
o
wn
Mo
de
and
C
l
ock
S
u
sp
end
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bur
s
t
Leng
t
h
= 4,
CAS
Lat
ency = 2
A
d
d
r
t
CK
S
P
t
C
KSP
CA
x
RA
x
RA
x
Ax
2
Ax
0
Ax
1
Ax
3
A
c
ti
v
a
te
C
o
mman
d
Ba
n
k
A
C
l
o
c
k S
u
sp
e
n
d
Mod
e
E
n
t
r
y
C
l
o
c
k S
u
sp
e
n
d
Mod
e
E
x
i
t
R
ead
C
o
m
m
and
B
ank
A
Cl
o
c
k
M
a
s
k
St
a
r
t
C
l
o
c
k M
a
sk
En
d
Pr
e
c
h
a
r
g
e
C
o
mmand
B
ank
A
P
o
we
r
Do
wn
Mod
e
E
n
t
r
y
P
o
we
r
Do
wn
Mo
de E
x
i
t
t
HZ
An
y
C
o
m
m
and
t
CK
2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
39
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
1
4
.
Au
t
o
Re
f
r
e
s
h
(
CBR)
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
A
d
d
r
Ax
0
Ax
1
Bur
s
t
Leng
t
h
= 4,
CAS
Lat
ency = 2
A
c
ti
v
a
te
C
o
mmand
Re
a
d
C
o
mma
nd
Pr
e
c
h
a
r
g
e
C
o
mman
d
A
u
to
Refr
es
h
C
o
mmand
A
u
to Refr
es
h
C
o
mman
d
t
RC
t
RP
t
RC
t
CK
2
A
l
l
B
ank
s
CA
x
RA
x
RA
x
Ba
n
k
A
B
ank
A
Ax
2
Ax
3
(
M
in
im
u
m
In
t
e
r
val)
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
40
\
CL
K
CKE
CS
DQ
RAS
CAS
WE
A11
(
BS)
DQM
15
. S
e
lf Ref
r
e
s
h
(
E
n
t
r
y
an
d
E
x
it
)
T2
T
3
T4
T0
T1
T6
T7
T8
T
9
T5
T1
1
T
TT
T1
0
T
T
TT
TT
T
T
Hi
-
Z
A10
A0 -
A9
A
l
l
B
ank
s
m
u
st
b
e
id
le
S
e
l
f
Refr
es
h
En
t
r
y
B
egi
n
S
e
l
f
R
e
fr
es
h
E
x
i
t
C
o
mma
nd
t
SR
EX
S
e
l
f
Refr
es
h
E
x
i
t
C
o
mma
nd i
s
s
ued
S
e
l
f
Refr
es
h
Ex
it
t
RC
t
CK
S
R
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
41
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
16.
1 R
a
nd
om
C
o
l
u
m
n
R
e
a
d
(P
ag
e wit
hin
sam
e B
a
n
k
) (
1
o
f
3)
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bur
s
t
Leng
t
h
= 4,
CAS
Lat
ency = 1
A
d
d
r
A
c
ti
v
a
te
C
o
mman
d
Ba
n
k
A
Pr
e
c
h
a
r
g
e
C
o
m
m
and
B
ank
A
CA
w
RA
w
RA
w
CA
x
Re
a
d
C
o
m
m
and
B
ank
A
CA
y
R
ead
C
o
mman
d
B
ank
A
A
c
ti
v
a
te
C
o
mm
and
B
a
n
k
A
RA
z
CA
z
R
ead
C
o
mma
nd
Ba
n
k
A
R
ead
C
o
m
m
and
B
a
n
k
A
RA
z
Aw
0
Aw
1
Aw
2
Aw
3
Ax
0
Ax
1
Ay
0
Ay
1
Az
0
Az
1
Az
2
Az
3
Ay
2
Ay
3
t
CK
1
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
42
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
16.
2 R
a
nd
om
C
o
l
u
m
n
R
e
a
d
(P
ag
e wit
hin
sam
e B
a
n
k
) (
2
o
f
3)
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bur
s
t
Leng
t
h
= 4,
CAS
Lat
ency = 2
A
d
d
r
A
c
ti
v
a
te
C
o
mman
d
Ba
n
k
A
CA
x
Re
a
d
C
o
mma
nd
Ba
n
k
A
CA
y
R
ead
C
o
m
m
and
B
ank
A
Aw
0
Aw
1
Aw
2
Aw
3
Ax
0
Ax
1
Ay
0
Ay
1
Az
0
Az
1
Az
2
Az
3
Ay
2
Ay
3
CA
w
Re
a
d
C
o
mm
and
B
ank
A
RA
w
RA
w
P
r
ec
har
ge
C
o
mm
and
Ba
n
k
A
A
c
ti
v
a
te
C
o
mmand
B
ank
A
CA
z
Re
a
d
C
o
mma
nd
Ba
n
k
A
RA
z
RA
z
t
CK
2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
43
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
16.
3 R
a
nd
om
C
o
l
u
m
n
R
e
a
d
(P
ag
e wit
hin
sam
e B
a
n
k
) (
3
o
f
3)
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bur
s
t
Leng
t
h
= 4,
CAS
Lat
ency = 3
A
d
d
r
A
c
ti
v
a
te
C
o
mman
d
Ba
n
k
A
CA
x
R
ead
C
o
mman
d
B
ank
A
CA
y
Re
a
d
C
o
mm
and
B
ank
A
Aw
0
Aw
1
Aw
2
Aw
3
Ax
0
Ax
1
Ay
0
Ay
1
Ay
2
Ay
3
CA
w
R
ead
C
o
mma
nd
Ba
n
k
A
RA
w
RA
w
Pr
e
c
h
a
r
g
e
C
o
m
m
and
B
ank
A
A
c
ti
v
a
te
C
o
mman
d
B
ank
A
CA
z
R
ead
C
o
mman
d
Ba
n
k
A
RA
z
RA
z
t
CK
3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
44
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
17.
1 R
a
nd
om
C
o
l
u
m
n
W
r
ite (
P
a
g
e w
i
thi
n
sa
m
e
B
a
nk)
(1 o
f
3
)
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bur
s
t
Leng
t
h
= 4,
CAS
Lat
ency = 1
A
d
d
r
RB
w
RB
w
CB
w
CB
x
A
c
ti
v
a
te
C
o
mma
nd
Ba
n
k
B
Wr
it
e
C
o
m
m
and
B
ank
B
Wr
it
e
C
o
mmand
B
ank
B
CB
y
Wr
it
e
C
o
mman
d
B
ank
B
RB
z
RB
z
P
r
e
c
har
ge
C
o
m
m
and
B
ank
B
Ac
t
i
v
a
t
e
C
o
mm
and
B
ank
B
CB
z
Wr
it
e
C
o
mman
d
B
ank
B
DB
w0
DB
w3
DB
w2
DB
w1
DB
x
1
DB
x
0
DB
y
0
DB
y
3
DB
y
2
DB
y
1
DB
z
0
DB
z
3
DB
z
2
DB
z
1
t
CK
1
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
45
CLK
CKE
CS
DQ
RAS
CAS
WE
A11(
BS)
DQM
18.1 R
a
ndo
m
R
o
w R
e
a
d
(I
nte
r
le
avin
g
B
a
n
ks)
(1 o
f
3)
T2
T
3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T1
6
T1
7
T1
8
T
1
9
T1
5
T
2
2
T2
0
T2
1
Hi
-
Z
A10
Bur
s
t
L
engt
h =
8,
CAS
Lat
enc
y
= 1
A0 -
A9
A
c
ti
v
a
te
C
o
mmand
B
ank
B
CB
x
RB
x
RB
x
CB
y
R
ead
C
o
mma
nd
Ba
n
k
B
R
ead
C
o
mma
nd
Ba
n
k
A
Re
a
d
C
o
m
m
and
B
ank
B
Bx
0
Bx
1
Bx
2
Bx
3
Bx
4
Bx
5
Bx
6
Bx
7
By
0
By
1
By
2
t
CK
1
Hi
g
h
t
RC
D
t
AC
1
t
RP
CA
x
RA
x
RA
x
RB
y
RB
y
A
c
ti
v
a
te
C
o
mm
and
B
ank
A
Pr
e
c
h
a
r
g
e
C
o
m
m
and
B
ank
B
A
c
ti
v
a
te
C
o
mm
and
B
ank
B
P
r
ec
har
ge
C
o
mm
and
B
ank
A
Ax
0
Ax
1
Ax
2
Ax
3
Ax
4
Ax
5
Ax
6
Ax
7
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
46
CLK
CKE
CS
DQ
RAS
CAS
WE
A11(
BS)
DQM
18.2 R
a
ndo
m
R
o
w R
e
a
d
(I
nte
r
le
avin
g
B
a
n
ks)
(2 o
f
3)
T2
T
3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T1
6
T1
7
T1
8
T
1
9
T1
5
T
2
2
T2
0
T2
1
Hi
-
Z
A10
Bur
s
t
L
engt
h =
8,
CAS
Lat
enc
y
= 2
A0 -
A9
CB
y
R
ead
C
o
mma
nd
Ba
n
k
B
R
ead
C
o
m
m
and
B
ank
A
Bx
0
Bx
1
Bx
2
Bx
3
Bx
4
Bx
5
Bx
6
Bx
7
By
0
By
1
t
CK
2
Hi
g
h
t
RCD
t
AC
2
t
RP
CA
x
P
r
ec
har
ge
C
o
mm
and
Ba
n
k
B
Ax
0
Ax
1
Ax
2
Ax
3
Ax
4
Ax
5
Ax
6
Ax
7
A
c
ti
v
a
te
C
o
mmand
B
ank
B
RB
x
RB
x
A
c
ti
v
a
te
C
o
mm
and
B
ank
A
RA
x
RA
x
CB
x
Re
a
d
C
o
mma
nd
Ba
n
k
B
A
c
ti
v
a
te
C
o
mman
d
B
ank
B
RB
y
RB
y
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
47
CLK
CKE
CS
DQ
RAS
CAS
WE
A11(
BS)
DQM
18. 3
R
a
nd
om
R
o
w R
e
a
d
(
I
nt
er
le
avin
g
B
a
n
ks)
(3 o
f
3
)
T2
T
3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T1
6
T1
7
T1
8
T
1
9
T1
5
T
2
2
T2
0
T2
1
Hi
-
Z
A10
Bur
s
t
L
engt
h =
8,
CAS
Lat
enc
y
= 3
A0 -
A9
CB
y
R
ead
C
o
mma
nd
Ba
n
k
B
By
0
t
CK
3
Hi
g
h
t
AC
3
A
c
ti
v
a
te
C
o
mmand
B
ank
B
RB
x
RB
x
A
c
ti
v
a
te
C
o
mm
and
B
ank
A
RA
x
RA
x
CB
x
R
ead
C
o
mman
d
Ba
n
k
B
Ac
t
i
v
a
t
e
C
o
mman
d
Ba
n
k
B
RB
y
RB
y
t
RCD
P
r
ec
ha
r
g
e
C
o
mman
d
B
ank
B
CA
x
Re
a
d
C
o
m
m
and
B
ank
A
t
RP
Bx
0
Bx
1
Bx
2
Bx
3
Bx
4
Bx
5
Bx
6
Bx
7
Ax
0
Ax
1
Ax
2
Ax
3
Ax
4
Ax
5
Ax
6
Ax
7
P
r
ec
har
ge
C
o
mm
and
B
ank
A
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
48
CLK
CKE
CS
DQ
RAS
CAS
WE
A11(
BS)
DQ
M
19.1
R
a
nd
om
R
o
w W
r
ite
(In
t
er
leavi
ng
B
a
nks
)
(1
of
3)
T2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T1
6
T1
7
T1
8
T
1
9
T1
5
T
2
2
T2
0
T2
1
Hi
-
Z
A10
Bu
r
s
t
Lengt
h =
8
,
CAS
L
a
te
n
c
y
=
1
A0 -
A9
t
CK
1
Hi
g
h
CA
x
RA
x
RA
x
Wr
it
e
C
o
mm
and
B
ank
A
t
RCD
A
c
ti
v
a
te
C
o
m
m
and
B
ank
A
CB
x
RB
x
RB
x
Wr
it
e
C
o
mman
d
B
ank
B
Ac
t
i
v
a
t
e
C
o
mma
nd
Ba
n
k
B
RA
y
RA
y
P
r
e
c
har
ge
C
o
m
m
and
B
ank
A
A
c
ti
v
a
te
C
o
mm
and
B
ank
A
t
RP
P
r
ec
har
ge
C
o
mm
and
B
ank
B
Wr
i
t
e
C
o
mman
d
B
ank
A
CA
y
DA
x
0
DA
x
3
DA
x
2
DA
x
1
DA
x
4
DA
x
7
DA
x
6
DA
x
5
DB
x
0
DB
x
3
DB
x
2
DB
x
1
DB
x
4
DB
x
7
DB
x
6
DB
x
5
DA
y
0
DA
y
3
DA
y
2
DA
y
1
t
DP
L
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
49
CLK
CKE
CS
DQ
RAS
CAS
WE
A11(
BS)
DQ
M
19.2
R
a
nd
om
R
o
w W
r
ite
(In
t
er
leavi
ng
B
a
nks
)
(2
of
3)
T2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T1
6
T1
7
T1
8
T
1
9
T1
5
T
2
2
T2
0
T2
1
Hi
-
Z
A10
Bu
r
s
t
Lengt
h =
8
,
CAS
L
a
te
n
c
y
=
2
A0 -
A9
t
CK
2
Hi
g
h
t
RCD
t
RP
Wr
it
e
C
o
mman
d
Ba
n
k
A
CA
y
DA
x
0
DA
x
3
DA
x
2
DA
x
1
DA
x
4
DA
x
7
DA
x
6
DA
x
5
DB
x
0
DB
x
3
DB
x
2
DB
x
1
DB
x
4
DB
x
7
DB
x
6
DB
x
5
DA
y
0
DA
y
3
DA
y
2
DA
y
1
t
DP
L
Wr
it
e
C
o
mman
d
Ba
n
k
A
CA
X
A
c
ti
v
a
te
C
o
m
m
and
B
ank
A
RA
x
RA
x
Ac
t
i
v
a
t
e
C
o
mma
nd
Ba
n
k
B
RB
x
RB
x
CB
x
P
r
ec
har
ge
C
o
mm
and
Ba
n
k
A
Wr
i
t
e
C
o
m
m
and
B
ank
B
A
c
ti
v
a
te
C
o
m
m
and
B
ank
A
RA
y
RA
y
CA
y
P
r
ec
ha
r
g
e
C
o
mman
d
B
ank
B
Wr
i
t
e
C
o
mma
nd
Ba
n
k
A
DA
y
4
t
DP
L
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
50
CLK
CKE
CS
DQ
RAS
CAS
WE
A11(
BS)
DQ
M
19.3
R
a
nd
om
R
o
w W
r
ite
(In
t
er
leavi
ng
B
a
nks
)
(3
of
3)
T2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T1
6
T1
7
T1
8
T
1
9
T1
5
T
2
2
T2
0
T2
1
Hi
-
Z
A10
Bu
r
s
t
Lengt
h =
8
,
CAS
L
a
te
n
c
y
=
3
A0 -
A9
t
CK
3
Hi
g
h
DA
x
0
DA
x
3
DA
x
2
DA
x
1
DA
x
4
DA
x
7
DA
x
6
DA
x
5
DB
x
0
DB
x
3
DB
x
2
DB
x
1
DB
x
4
DB
x
7
DB
x
6
DB
x
5
DA
y
2
DA
y
1
DA
y
0
Wr
it
e
C
o
m
m
and
B
ank
A
CA
X
A
c
ti
v
a
te
C
o
m
m
and
B
ank
A
RA
x
RA
x
Ac
t
i
v
a
t
e
C
o
mma
nd
Ba
n
k
B
RB
x
RB
x
Ac
t
i
v
a
t
e
C
o
mmand
B
ank
A
RA
y
RA
y
DA
y
3
t
DP
L
CB
x
Wr
it
e
C
o
mm
and
Ba
n
k
B
Pr
e
c
h
a
r
g
e
C
o
m
m
and
B
ank
A
Wr
i
t
e
C
o
mman
d
B
ank
A
CA
y
P
r
ec
har
ge
C
o
mm
and
Ba
n
k
B
t
RP
t
DP
L
t
RCD
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
51
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
17.
2 R
a
nd
om
C
o
l
u
m
n
W
r
ite (
P
a
g
e w
i
thi
n
sa
m
e
B
a
nk)
(2 o
f
3
)
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bur
s
t
Leng
t
h
= 4,
CAS
Lat
ency = 2
A
d
d
r
CB
x
Wr
i
t
e
C
o
mma
nd
Ba
n
k
B
CB
y
Wr
i
t
e
C
o
m
m
and
B
ank
B
P
r
ec
har
ge
C
o
mm
and
B
ank
B
DB
w0
DB
w3
DB
w2
DB
w
1
DB
x
1
DB
x
0
DB
y
0
DB
y
3
DB
y
2
DB
y
1
DB
z
0
DB
z
3
DB
z
2
DB
z
1
t
CK
2
A
c
ti
v
a
te
C
o
mmand
B
ank
B
CA
x
Wr
i
t
e
C
o
mma
nd
Ba
n
k
B
RA
w
RA
w
A
c
ti
v
a
te
C
o
mmand
B
ank
B
CB
z
Wr
i
t
e
C
o
mma
nd
Ba
n
k
B
RB
z
RB
z
A
c
ti
v
a
te
C
o
mman
d
Ba
n
k
B
CB
z
Wr
it
e
C
o
mm
and
B
ank
B
RB
z
RB
z
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
52
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
17.
3 R
a
nd
om
C
o
l
u
m
n
W
r
ite (
P
a
g
e w
i
thi
n
sa
m
e
B
a
nk)
(3 o
f
3
)
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bur
s
t
Leng
t
h
= 4,
CAS
Lat
ency = 3
A
d
d
r
CB
x
Wr
it
e
C
o
mman
d
B
ank
B
CB
y
Wr
it
e
C
o
mm
and
B
ank
B
Pr
e
c
h
a
r
g
e
C
o
mmand
B
ank
B
DB
w0
DB
w3
DB
w2
DB
w1
DB
x
1
DB
x
0
DB
y
0
DB
y
3
DB
y
2
DB
y
1
DB
z
0
DB
z
1
t
CK
3
A
c
ti
v
a
te
C
o
mman
d
B
ank
B
CB
z
Wr
it
e
C
o
mman
d
Ba
n
k
B
RB
z
RB
z
A
c
ti
v
a
te
C
o
mman
d
Ba
n
k
B
CB
z
Wr
i
t
e
C
o
mma
nd
Ba
n
k
B
RB
z
RB
z
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
53
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
20.
1 Fu
ll P
a
ge
R
ead
C
ycle
(1 o
f
3)
T
2
T3
T4
T0
T1
T
T
TT
T
T
T
TT
T
TT
T
T
TT
TT
Hi
-
Z
AP
Bur
s
t
Le
ngt
h
=
Ful
l
Pag
e
,
CAS
Lat
ency = 1
A
d
d
r
t
CK
1
RB
x
RA
x
RB
x
CA
x
RA
x
Hi
g
h
R
ead
C
o
mman
d
Ba
n
k
A
A
c
ti
v
a
te
C
o
mm
and
B
ank
A
A
c
ti
v
a
te
C
o
m
m
and
B
ank
B
Ax
Ax
+
1
Ax
-
1
Ax
-
2
Ax
+
2
Ax
Bx
Bx
+
1
Bx
+
5
Bx
+
4
Bx
+
3
Bx
+
2
Bx
+
7
Bx
+
6
CB
x
R
ead
C
o
mman
d
B
ank
B
RB
y
RB
y
P
r
ec
har
ge
C
o
mm
and
B
ank
B
A
c
ti
v
a
te
C
o
m
m
and
B
ank
B
Bu
r
s
t
St
o
p
C
o
mm
and
F
u
l
l
P
age
bur
s
t
o
per
ati
o
n doe
s
no
t
ter
m
i
n
a
t
e w
hen
the bu
r
s
t l
ength i
s
s
a
ti
s
f
i
ed;
Ax
+
1
t
RP
t
RRD
the bur
s
t
c
o
unter
i
n
c
r
eme
n
ts
and c
onti
nues
T
he bu
r
s
t c
ounter
w
r
aps
f
r
om
the h
i
ghe
s
t
or
de
r
page
addr
es
s
b
a
c
k
to z
e
r
o
d
u
r
i
ng t
h
i
s
ti
m
e
i
n
ter
v
al
.
bur
s
t
i
ng be
gi
nn
i
ng
w
i
th t
he s
t
ar
ti
ng
addr
es
s
.
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
54
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
20.
2 Fu
ll P
a
ge
R
ead
C
ycle
(2 o
f
3)
T
2
T3
T4
T0
T1
T6
T
TT
T5
T
T
TT
T
TT
T
T
TT
TT
Hi
-
Z
AP
Bur
s
t
Le
ngt
h
=
Ful
l
Pag
e
,
CAS
Lat
ency = 2
A
d
d
r
t
CK
2
Hi
g
h
Ax
Ax
+
1
Ax
-
1
Ax
-
2
Ax
+
2
Ax
Bx
Bx
+
1
Bx
+
5
Bx
+
4
Bx
+
3
Bx
+
2
Ax
+
1
Bx
+
6
CB
x
R
ead
C
o
m
m
and
B
ank
B
P
r
ec
har
ge
C
o
mm
and
B
ank
B
Bu
r
s
t
St
o
p
C
o
mm
and
CA
x
R
ead
C
o
m
m
and
B
ank
A
A
c
ti
v
a
te
C
o
mm
and
B
ank
A
RA
x
RA
x
A
c
ti
v
a
te
C
o
mma
nd
Ba
n
k
B
RB
x
RB
x
Ac
t
i
v
a
t
e
C
o
m
m
and
B
ank
B
RB
y
RB
y
t
RP
F
u
l
l
P
age b
u
r
s
t op
er
a
t
i
o
n
does
not
te
r
m
i
nate
w
hen th
e bur
s
t
l
e
n
g
th i
s
s
a
ti
s
f
i
ed;
th
e bur
s
t
c
o
u
n
ter
i
n
c
r
emen
ts
a
nd c
onti
nues
T
he bur
s
t
c
o
unter
w
r
aps
fr
om
the hi
ghes
t or
der
page
addr
es
s
ba
c
k
to z
e
r
o
du
r
i
ng th
i
s
ti
m
e
i
n
t
e
r
v
al
.
bu
r
s
ti
n
g
begi
nni
ng w
i
th the
s
t
a
r
ti
ng ad
dr
es
s
.
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
55
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
20.
3 Fu
ll P
a
ge
R
ead
C
ycle
(3 o
f
3)
T
2
T3
T4
T0
T1
T6
T7
T8
T
T5
T
T
TT
T
TT
T
T
TT
TT
Hi
-
Z
AP
Bur
s
t
Le
ngt
h
=
Ful
l
Pag
e
,
CAS
Lat
ency = 3
A
d
d
r
t
CK
3
Hi
g
h
Ax
Ax
+
1
Ax
-
1
Ax
-
2
Ax
+
2
Ax
Bx
Bx
+
1
Bx
+
5
Bx
+
4
Bx
+
3
Bx
+
2
Ax
+
1
CB
x
Re
a
d
C
o
mm
and
B
ank
B
P
r
ec
har
ge
C
o
mm
and
B
ank
B
Bu
r
s
t
St
o
p
C
o
mm
and
CA
x
Re
a
d
C
o
mm
and
B
ank
A
A
c
ti
v
a
te
C
o
mm
and
B
ank
A
RA
x
RA
x
A
c
ti
v
a
te
C
o
mmand
B
ank
B
RB
x
RB
x
Ac
t
i
v
a
t
e
C
o
mm
and
Ba
n
k
B
RB
y
RB
y
t
RRD
F
u
l
l
P
age
bur
s
t
oper
ati
on doe
s
no
t
T
he b
u
r
s
t c
ount
er
w
r
ap
s
fr
om the
hi
g
hes
t
or
der
pa
ge add
r
e
s
s
bac
k
to
z
e
r
o
dur
i
n
g
thi
s
ti
me i
n
ter
v
a
l
.
ter
m
i
n
a
t
e w
hen
the l
ength
i
s
s
a
ti
s
f
i
ed;
the bu
r
s
t c
ounter
i
n
c
r
ements
and
c
o
nti
n
u
e
s
bur
s
t
i
ng be
gi
nn
i
n
g
w
i
th
the s
t
ar
ti
ng
addr
es
s
.
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
56
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
21.
1 Fu
ll P
a
ge
W
r
it
e C
ycle
(1
of 3
)
T
2
T3
T4
T0
T1
T
T
TT
T
T
T
TT
T
TT
T
T
TT
TT
Hi
-
Z
AP
Bur
s
t
Le
ngt
h
=
Ful
l
Pag
e
,
CAS
Lat
ency = 1
A
d
d
r
t
CK
1
RB
x
RA
x
RB
x
CA
x
RA
x
Hi
g
h
Wr
i
t
e
C
o
mman
d
Ba
n
k
A
A
c
ti
v
a
te
C
o
mm
and
B
ank
A
A
c
ti
v
a
te
C
o
m
m
and
B
ank
B
DA
x
DA
x
+
1
DA
x
-
1
DA
x
+
2
DA
x
+
2
DA
x
DB
x
DB
x
+
1
CB
x
Wr
it
e
C
o
mmand
B
ank
B
RB
y
RB
y
P
r
ec
har
ge
C
o
mm
and
B
ank
B
A
c
ti
v
a
te
C
o
m
m
and
B
ank
B
Bu
r
s
t
St
o
p
C
o
mm
and
DA
x
+
1
P
age L
ength:
2M
b x
4I/O
x
2
B
a
n
k
s
=
1024
1M
b x
8I/O
x
2
B
a
n
k
s
=
512
51
2k
b
x
1
6
I/O
x
2
B
ank
s
=
256
Data
i
s
i
g
n
o
r
e
d.
DB
x
+
3
DB
x
+
2
DB
x
+
4
DB
x
+
5
DB
x
+
6
DB
x
+
7
F
u
l
l
P
age bu
r
s
t op
er
a
t
i
o
n
does
not
ter
m
i
nate
w
hen th
e bur
s
t
l
e
n
g
th i
s
s
a
ti
s
f
i
ed;
the
bur
s
t
c
o
u
n
ter
i
n
c
r
emen
ts
an
d c
onti
n
ues
T
he bur
s
t
c
ount
er
w
r
ap
s
fr
om the
hi
g
hes
t or
der
pa
ge add
r
e
s
s
bac
k
to
z
e
r
o
dur
i
n
g thi
s
ti
me i
n
ter
v
al
.
bu
r
s
ti
n
g
begi
nni
ng w
i
th the
s
t
a
r
ti
ng ad
dr
es
s
.
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
57
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
21.
2 Fu
ll P
a
ge
W
r
it
e C
ycle
(2
of 3
)
T
2
T3
T4
T0
T1
T
T
TT
T5
T
T
TT
T
TT
T
T
TT
TT
Hi
-
Z
AP
Bur
s
t
Le
ngt
h
=
Ful
l
Pag
e
,
CAS
Lat
ency = 2
A
d
d
r
t
CK
2
Hi
g
h
CB
x
Wr
it
e
C
o
m
m
and
B
ank
B
P
r
ec
har
ge
C
o
mm
and
B
ank
B
Bu
r
s
t
St
o
p
C
o
mm
and
CA
x
Wr
it
e
C
o
m
m
and
B
ank
A
A
c
ti
v
a
te
C
o
mm
and
B
ank
A
RA
x
RA
x
A
c
ti
v
a
te
C
o
mma
nd
Ba
n
k
B
RB
x
RB
x
Ac
t
i
v
a
t
e
C
o
m
m
and
B
ank
B
RB
y
RB
y
D
a
ta i
s
i
gnor
ed.
DA
x
DA
x
+
1
DA
x
-
1
DA
x
+
3
DA
x
+
2
DA
x
DB
x
DB
x
+
1
DA
x
+
1
DB
x
+
3
DB
x
+
2
DB
x
+
4
DB
x
+
5
DB
x
+
6
F
u
l
l
P
a
g
e
bur
s
t
oper
ati
on do
es
not
ter
m
i
nate w
h
en the
bur
s
t
l
engt
h i
s
s
a
ti
s
f
i
e
d;
the b
u
r
s
t c
ounte
r
i
n
c
r
e
m
ents
and
c
o
n
t
i
n
u
e
s
T
he b
u
r
s
t c
ount
er
w
r
ap
s
fr
om the
hi
g
hes
t
or
der
pa
ge add
r
e
s
s
bac
k
to
z
e
r
o
dur
i
n
g thi
s
ti
me i
n
ter
v
a
l
.
bur
s
t
i
n
g
be
g
i
nni
n
g
wi
th
the s
t
ar
ti
n
g
addr
es
s
.
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
58
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
21.
3 Fu
ll P
a
ge
W
r
it
e C
ycle
(3
of 3
)
T
2
T3
T4
T0
T1
T6
T
TT
T5
T
T
TT
T
TT
T
T
TT
TT
Hi
-
Z
AP
Bur
s
t
Le
ngt
h
=
Ful
l
Pag
e
,
CAS
Lat
ency = 3
A
d
d
r
t
CK
3
Hi
g
h
CB
x
Wr
it
e
C
o
mm
and
B
ank
B
P
r
ec
har
ge
C
o
mm
and
B
ank
B
Bu
r
s
t
St
o
p
C
o
mm
and
CA
x
Wr
i
t
e
C
o
mm
and
B
ank
A
A
c
ti
v
a
te
C
o
mm
and
B
ank
A
RA
x
RA
x
A
c
ti
v
a
te
C
o
mmand
B
ank
B
RB
x
RB
x
Ac
t
i
v
a
t
e
C
o
mm
and
Ba
n
k
B
RB
y
RB
y
DA
x
DA
x
+
1
DA
x
-
1
DA
x
+
3
DA
x
+
2
DA
x
DB
x
DB
x
+
1
DA
x
+
1
DB
x
+
3
DB
x
+
2
DB
x
+
4
DB
x
+
5
F
u
l
l
P
age
bur
s
t
o
per
ati
o
n does
not
T
he
bur
s
t
c
oun
ter
w
r
a
p
s
fr
om the
hi
g
hes
t or
der
pa
ge ad
dr
e
s
s
bac
k
t
o
z
e
r
o
dur
i
n
g thi
s
ti
me i
n
ter
v
al
.
t
e
r
m
i
n
a
t
e w
hen
the l
ength
i
s
s
a
ti
s
f
i
ed; t
he bur
s
t
c
o
unter
i
n
c
r
e
m
ents
and
c
o
n
t
i
nue
s
b
u
r
s
ti
ng beg
i
n
n
i
ng w
i
th
t
he s
t
ar
ti
ng
addr
es
s
.
D
a
ta i
s
i
gnor
ed
.
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
59
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
22.
1 P
r
ec
har
g
e
Ter
m
in
at
ion
of
a B
u
r
s
t
(1 o
f
3)
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bu
r
st
L
engt
h =
Ful
l
Pa
ge,
C
A
S
Lat
ency
= 1
A
d
d
r
t
CK
1
RA
x
RA
x
CA
x
Wr
i
t
e
C
o
mm
and
B
a
n
k
A
A
c
ti
v
a
te
C
o
m
m
and
B
ank
A
Pr
e
c
h
a
r
g
e
C
o
mmand
B
ank
A
DA
x
0
DA
x
4
DA
x
3
DA
x
2
DA
x
1
P
r
ec
har
ge T
e
r
m
i
nati
o
n
o
f
a W
r
i
t
e B
u
r
s
t.
W
r
i
t
e data
i
s
mas
k
ed
.
RA
y
RA
y
CA
y
A
c
ti
v
a
te
C
o
m
m
and
B
ank
A
R
ead
C
o
m
m
and
B
ank
A
Ay
0
Ay
1
Ay
2
P
r
ec
h
a
r
g
e
T
e
r
m
i
nati
on of
a
R
ead B
u
r
s
t.
P
r
ec
har
ge
C
o
mm
and
Ba
n
k
A
A
c
ti
v
a
te
C
o
mma
nd
B
a
n
k
A
Wr
it
e
C
o
mmand
B
ank
A
DA
z
0
DA
z
3
DA
z
2
DA
z
1
t
RP
t
RP
DA
z
4
DA
z
7
DA
z
6
DA
z
5
RA
z
RA
z
CA
z
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
60
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
22.
2 P
r
ec
har
g
e
Ter
m
in
at
ion
of
a B
u
r
s
t
(2 o
f
3)
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bu
r
st
Le
ngt
h
=
8
o
r
Ful
l
Pa
ge,
CAS Lat
ency = 2
A
d
d
r
t
CK
2
P
r
ec
har
ge
C
o
m
m
and
B
ank
A
DA
x
0
DA
x
3
DA
x
2
DA
x
1
P
r
ec
h
a
r
g
e T
e
r
m
i
n
at
i
o
n
o
f
a W
r
i
t
e B
u
r
s
t
.
W
r
i
t
e
data i
s
m
a
s
k
ed.
Ay
0
Ay
1
Ay
2
P
r
ec
har
ge T
e
r
m
i
nati
o
n
of a
R
ead B
u
r
s
t.
P
r
ec
har
ge
C
o
mm
and
Ba
n
k
A
t
RP
A
c
ti
v
a
te
C
o
mm
and
B
ank
A
RA
x
RA
x
Wr
it
e
C
o
m
m
and
B
ank
A
CA
x
CA
y
Re
a
d
C
o
mm
and
B
ank
A
Hi
g
h
A
c
ti
v
a
te
C
o
mman
d
B
ank
A
RA
y
RA
y
t
RP
A
c
ti
v
a
te
C
o
mmand
B
ank
A
RA
z
RA
z
CA
z
Re
a
d
C
o
mma
nd
Ba
n
k
A
Az
0
Az
1
Az
2
P
r
ec
har
ge
C
o
mma
nd
Ba
n
k
A
t
RP
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
61
\
CLK
CKE
CS
DQ
RAS
CAS
WE
B
A
DQM
22.
3 P
r
ec
har
g
e
Ter
m
in
at
ion
of
a B
u
r
s
t
(3 o
f
3)
T
2
T3
T4
T0
T1
T6
T7
T8
T9
T5
T1
1
T1
2
T1
3
T
1
4
T1
0
T
1
6
T
17
T
1
8
T
19
T1
5
T
2
2
T2
0
T
2
1
Hi
-
Z
AP
Bu
r
st
Lengt
h =
4,
8 o
r
F
u
ll P
a
g
e
,
C
A
S
Lat
ency
= 3
A
d
d
r
t
CK
3
Pr
e
c
h
a
r
g
e
C
o
mmand
B
ank
A
DA
x
0
P
r
e
c
ha
r
g
e
T
e
r
m
i
nat
i
on
of a
W
r
i
t
e B
u
r
s
t.
Wr
i
t
e
D
a
t
a
is
m
a
s
k
e
d
Ay
0
Ay
1
Ay
2
P
r
ec
har
ge T
e
r
m
i
nati
o
n
Pr
e
c
h
a
r
g
e
C
o
m
m
and
B
ank
A
t
RP
A
c
ti
v
a
te
C
o
mm
and
B
ank
A
RA
x
RA
x
Wr
i
t
e
C
o
mm
and
B
ank
A
CA
x
CA
y
R
ead
C
o
mman
d
Ba
n
k
A
Hi
g
h
A
c
ti
v
a
te
C
o
mman
d
B
ank
A
RA
y
RA
y
t
RP
A
c
ti
v
a
te
C
o
mman
d
B
ank
A
RA
z
RA
z
of a
R
ead B
u
r
s
t.
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
62
Complete List of Operation Commands
SDRAM FUNCTION TRUTH TABLE
CURRENT
STATE
1
CS
RAS
CAS
WE
BS
Addr
ACTION
Idle
H
L
L
L
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
L
H
H
L
L
X
H
L
X
H
L
H
L
X
X
BS
BS
BS
BS
X
Op-
X
X
X
X
RA
AP
X
Code
NOP or Power Down
NOP
ILLEGAL
2
ILLEGAL
2
Row (&Bank) Active; Latch Row Address
NOP
4
Auto-Refresh or Self-Refresh
5
Mode reg. Access
5
Row Active
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
L
L
H
H
L
X
X
H
L
H
L
X
X
X
BS
BS
BS
BS
X
X
X
CA,AP
CA,AP
X
AP
X
NOP
NOP
Begin Read; Latch CA; DetermineAP
Begin Write; Latch CA; DetermineAP
ILLEGAL
2
Precharge
ILLEGAL
Read
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
BS
BS
BS
X
X
X
X
CA,AP
CA,AP
X
AP
X
NOP (Continue Burst to End;>Row Active)
NOP (Continue Burst to End;>Row Active)
Burst Stop Command > Row Active
Term Burst, New Read, DetermineAP
3
Term Burst, Start Write, DetermineAP
3
ILLEGAL
2
Term Burst, Precharge
ILLEGAL
Write
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
BS
BS
BS
X
X
X
X
CA,AP
CA,AP
X
AP
X
NOP (Continue Burst to End;>Row Active)
NOP (Continue Burst to End;>Row Active)
Burst Stop Command > Row Active
Term Burst, Start Read, DetermineAP
3
Term Burst, New Write, DetermineAP
3
ILLEGAL
2
Term Burst, Precharge
3
ILLEGAL
Read
with
Auto
Precharge
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
X
BS
BS
X
X
X
X
X
X
X
AP
X
NOP (Continue Burst to End;> Precharge)
NOP (Continue Burst to End;> Precharge)
ILLEGAL
2
ILLEGAL
2
ILLEGAL
ILLEGAL
2
ILLEGAL
2
ILLEGAL
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
63
SDRAM FUNCTION TRUTH TABLE(continued)
CURRENT
STATE
1
CS
RAS
CAS
WE
BS
Addr
ACTION
Write
with
Auto
Precharge
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
X
BS
BS
X
X
X
X
X
X
X
AP
X
NOP (Continue Burst to End;> Precharge)
NOP (Continue Burst to End;> Precharge)
ILLEGAL
2
ILLEGAL
2
ILLEGAL
ILLEGAL
2
ILLEGAL
2
ILLEGAL
Precharging
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
X
X
BS
BS
BS
BS
X
X
X
X
X
X
AP
X
NOP;> Idle after tRP
NOP;> Idle after tRP
ILLEGAL
2
ILLEGAL
2
ILLEGAL
2
NOP
4
ILLEGAL
Row
Activating
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
X
X
BS
BS
BS
BS
X
X
X
X
X
X
AP
X
NOP;> Row Active after tRCD
NOP;> Row Active after tRCD
ILLEGAL
2
ILLEGAL
2
ILLEGAL
2
ILLEGAL
2
ILLEGAL
Write
Recovering
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
X
X
BS
BS
BS
BS
X
X
X
X
X
X
AP
X
NOP
NOP
ILLEGAL
2
ILLEGAL
2
ILLEGAL
2
ILLEGAL
2
ILLEGAL
Refreshing
H
L
L
L
L
X
H
H
L
L
X
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP;> Idle after tRC
NOP;> Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
Mode
Register
Accessing
H
L
L
L
L
X
H
H
H
L
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
NOP
NOP
ILLEGAL
ILLEGAL
ILLEGAL
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
64
CLOCK ENABLE (CKE) TRUTH TABLE:
ABBREVIATIONS:
RA = Row Address BS = Bank Address
CA = Column Address AP = Auto Precharge
Notes for SDRAM function truth table :
1. Current State is state of the bank determined by BS. All entries assume that CKE was active (HIGH) during the preced
ing clock
cycle.
2. Illegal to bank in specified state; Function may be legal in the bank indicated by BS, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in Idle state. May precharge bank(s) indicated by BS (andAP).
5. Illegal if any bank is not Idle.
6. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before
any
command other than EXIT.
7. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
8. Must be legal command as defined in the SDRAM function truth table.
STATE(n)
CKE
n-1
CKE
n
CS
RAS
CAS
WE
Addr
ACTION
Self-
Refresh
6
H
L
L
L
L
L
L
X
H
H
H
H
H
L
X
H
L
L
L
L
X
X
X
H
H
H
L
X
X
X
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
INVALID
EXIT Self-Refresh, Idle after tRC
EXIT Self-Refresh, Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self-Refresh)
Power-Down
H
L
L
L
L
L
L
X
H
H
H
H
H
L
X
H
L
L
L
L
X
X
X
H
H
H
L
X
X
X
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
INVALID
EXIT Power-Down, > Idle.
EXIT Power-Down, > Idle.
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low-Power Mode)
All. Banks
Idle
7
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
X
H
L
L
L
L
L
L
X
X
X
H
H
H
L
L
L
X
X
X
H
H
L
H
L
L
X
X
X
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
Refer to the function truth table
Enter Power- Down
Enter Power- Down
ILLEGAL
ILLEGAL
ILLEGAL
Enter Self-Refresh
ILLEGAL
NOP
Any State
other than
listed above
H
H
L
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Refer to the function truth table
Begin Clock Suspend next cycle
8
Exit Clock Suspend next cycle
8
.
Maintain Clock Suspend.
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