Semiconductor Group
1
2M x 32-Bit Dynamic RAM Module
HYM 322030S/GS-50/-60/-70
Advanced Information
2 097 152 words by 32-bit organization
1 memory bank
Fast access and cycle time
50 ns access time
90 ns cycle time (-50 version)
60 ns access time
110 ns cycle time (-60 version)
70 ns access time
130 ns cycle time (-70 version)
Fast page mode capability
35 ns cycle time (-50 version)
40 ns cycle time (-60 version)
45 ns cycle time (-70 version)
Single + 5 V (
10 %) supply
Low power dissipation
max. 2640 mW active (-50 version)
max. 2420 mW active (-60 version)
max. 2200 mW active (-70 version)
CMOS 22 mW standby
TTL
44 mW standby
CAS-before-RAS refresh
RAS-only-refresh
Hidden-refresh
4 decoupling capacitors mounted on substrate
All inputs, outputs and clocks fully TTL compatible
72 pin Single in-Line Memory Module (L-SIM-72-9 ) with 20.32 mm (800 mil) height
Utilizes four 2M
8 -DRAMs in 400 mil SOJ packages
2048 refresh cycles / 32 ms with 11/10 addressing
Optimized for use in byte-write non-parity applications
Tin-Lead contact pads (S-version)
Gold contact pads (GS - version)
Semicunductor Group
9.95
Semiconductor Group
2
HYM 322030S/GS-50/-60/-70
2M
32-Bit
The HYM 322030S/GS-50/-60/-70 is a 8 MByte DRAM module organized as 2 097 152 words by
32-bit in a 72-pin single-in-line package comprising four HYB 5117800BSJ 2M
8 DRAMs in 400
mil wide SOJ-packages mounted together with four 0.2
F ceramic decoupling capacitors on a PC
board.
Each HYB 5117800BSJ is described in the data sheet and is fully electrical tested and processed
according to SIEMENS standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 322030S/GS-60/-70 dictates the use of early write cycles.
Ordering Information
Type
Ordering Code
Package
Description
HYM 322030S-50
on request
L-SIM-72-9
DRAM Module
(access time 50 ns)
HYM 322030S-60
Q67100-Q976
L-SIM-72-9
DRAM Module
(access time 60 ns)
HYM 322030S-70
Q67100-Q977
L-SIM-72-9
DRAM Module
(access time 70 ns)
HYM 322030GS-50
on request
L-SIM-72-9
DRAM Module
(access time 50 ns)
HYM 322030GS-60
Q67100-Q2018
L-SIM-72-9
DRAM Module
(access time 60 ns)
HYM 322030GS-70
Q67100-Q2019
L-SIM-72-9
DRAM Module
(access time 70 ns)
Semiconductor Group
3
HYM 322030S/GS-50/-60/-70
2M
32-Bit
Pin Configuration
VSS 1 DQ0 2
DQ16 3 DQ1 4
DQ17 5 DQ2 6
DQ18 7 DQ3 8
DQ19 9 VCC 10
N.C. 11 A0 12
A1 13 A2 14
A3 15 A4 16
A5 17 A6 18
A10 19 DQ4 20
DQ20 21 DQ5 22
DQ21 23 DQ6 24
DQ22 25 DQ7 26
DQ23 27 A7 28
N.C. 29 VCC 30
A8 31 A9 32
N.C. 33 RAS2 34
N.C. 35 N.C. 36
N.C. 37 N.C. 38
VSS 39 CAS0 40
CAS2 41 CAS3 42
CAS1 43 RAS0 44
N.C. 45 N.C. 46
WE 47 N.C. 48
DQ8 49 DQ24 50
DQ9 51 DQ25 52
DQ10 53 DQ26 54
DQ11 55 DQ27 56
DQ12 57 DQ28 58
VCC 59 DQ29 60
DQ13 61 DQ30 62
DQ14 63 DQ31 64
DQ15 65 N.C. 66
PD0 67 PD1 68
PD2 69 PD3 70
N.C. 71 VSS 72
Pin Names
Presence Detect Pins
A0R-A10R
Row Address Inputs
A0C-A9C
Column Address Inputs
DQ0-DQ31
Data Input/Output
CAS0 - CAS3
Column Address Strobe
RAS0, RAS2
Row Address Strobe
WE
Read/Write Input
V
CC
Power (+ 5 V)
V
SS
Ground
PD
Presence Detect Pin
N.C.
No Connection
-50
-60
-70
PD0
N.C.
N.C.
N.C.
PD1
N.C.
N.C.
N.C.
PD2
V
SS
N.C.
V
SS
PD3
V
SS
N.C.
N.C.
Semiconductor Group
4
HYM 322030S/GS-50/-60/-70
2M
32-Bit
Block Diagram
CAS RAS
CAS0
RAS0
I/O1-I/O8
DQ0-DQ7
OE
D1
CAS RAS
CAS1
I/O1-I/O8
DQ8-DQ15
OE
D2
CAS RAS
CAS2
RAS2
I/O1-I/O8
DQ16-DQ23
OE
D3
CAS RAS
CAS3
I/O1-I/O8
DQ24-DQ31
OE
D4
A0R - A10R,
A0C - A9C
D1 - D4
WE
D1 - D4
VCC
VSS
C1 - C 4
Semiconductor Group
5
HYM 322030S/GS-50/-60/-70
2M
32-Bit
Absolute Maximum Ratings
Operation temperature range ......................................................................................... 0 to + 70 C
Storage temperature range......................................................................................... 55 to 125 C
Input/output voltage ............................................................................0.5V to min (Vcc+0.5, 7.0) V
Power supply voltage...................................................................................................... 1 to + 7 V
Power dissipation..................................................................................................................... 4.2 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
T
A
= 0 to 70 C,
V
CC
= 5 V
10 %
Parameter
Symbol
Limit Values
Unit
Test
Condition
min.
max.
Input high voltage
V
IH
2.4
Vcc+0.5
V
1)
Input low voltage
V
IL
0.5
0.8
V
1)
Output high voltage (
I
OUT
= 5 mA)
V
OH
2.4
V
1)
Output low voltage (
I
OUT
= 4.2 mA)
V
OL
0.4
V
1)
Input leakage current
(0 V <
V
IN
< 6.5 V, all other pins = 0 V)
I
I(L)
10
10
A
1)
Output leakage current
(DO is disabled, 0 V <
V
OUT
< 5.5 V)
I
O(L)
10
10
A
1)
Average
V
CC
supply current
(RAS, CAS, address cycling,
t
RC
=
t
RC
min)
-50 version
-60 version
-70 version
I
CC1
480
440
400
mA
mA
mA
2),3),4)
Standby
V
CC
supply current
(RAS = CAS =
V
IH
)
I
CC2
8
mA
Average
V
CC
supply current
during RAS only refresh cycles
(RAS cycling, CAS =
V
IH
,
t
RC
=
t
RC
min)
-50 version
-60 version
-70 version
I
CC3
480
440
400
mA
mA
mA
2), 4)
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