Semiconductor Group
571
09.94
4M x 32-Bit Dynamic RAM Module
Preliminary Information
HYM 324020S/GS-60/-70
4 194 304 words by 32-bit organization
(alternative 8 388 608 words by 16-bit)
Fast access and cycle time
60 ns access time
110 ns cycle time (-60 version)
70 ns access time
130 ns cycle time (-70 version)
Fast page mode capability
40 ns cycle time (-60 version)
45 ns cycle time (-70 version)
Single + 5 V (
10 %) supply
Low power dissipation
max. 4840 mW active
(HYM 324020S/GS-60)
max. 4400 mW active
(HYM 324020S/GS-70)
CMOS 44 mW standby
TTL
88 mW standby
Ordering Information
Type
Ordering Code
Package
Description
HYM 324020S-60
Q67100-Q979
L-SIM-72-12
DRAM Module
(access time 60 ns)
HYM 324020S-70
Q67100-Q980
L-SIM-72-12
DRAM Module
(access time 70 ns)
HYM 324020GS-60
Q67100-Q2005
L-SIM-72-12
DRAM Module
(access time 60 ns)
HYM 324020GS-70
on request
L-SIM-72-12
DRAM Module
(access time 70 ns)
CAS-before-RAS refresh
RAS-only-refresh
Hidden-refresh
8 decoupling capacitors mounted on
substrate
All inputs, outputs and clocks fully TTL
compatible
72 pin Single in-Line Memory Module with
22.86 mm (900 mil) height
Utilizes eight 4Mx4-DRAMs in 300mil wide
SOJ-packages
2048 refresh cycles / 32 ms
Tin-Lead contact pads (S - version)
Gold contact pads (GS - version)
Semiconductor Group
572
HYM 324020S/GS-60/-70
4M x 32-Bit
The HYM 324020S/GS-60/-70 is a 16 M Byte DRAM module organized as 4 194 304 words by
32-bit in a 72-pin single-in-line package comprising eight HYB 5117400BJ 4M x 4 DRAMs in 300
mil wide SOJ-packages mounted together with eight 0.2
F ceramic decoupling capacitors on a PC
board.
The HYM 324020S/GS-60/-70 can also be used as a 8 388 608 words by 16-bits dynamic RAM
module by means of connecting DQ0 and DQ16, DQ1 and DQ17, DQ2 and DQ18, ..., DQ15 and
DQ31, respectively.
Each HYB 5117400BJ is described in the data sheet and is fully electrical tested and processed
according to SIEMENS standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 324020S/GS-60/-70 dictates the use of early write cycles.
Pin Definitions and Functions
Presence Detect Pins
Pin No.
Functions
A0-A10
Address Inputs for
HYM 324020S/GS
DQ0-DQ31
Data Input/Output
CAS0 - CAS3
Column Address Strobe
RAS0, RAS2
Row Address Strobe
WE
Read/Write Input
V
CC
Power (+ 5 V)
V
SS
Ground
PD
Presence Detect Pin
N.C.
No Connection
-60
-70
PD0
V
SS
V
SS
PD1
N.C.
N.C.
PD2
N.C.
V
SS
PD3
N.C.
N.C.
Semiconductor Group
573
HYM 324020S/GS-60/-70
4M x 32-Bit
Pin Configuration
(top view)
Semiconductor Group
574
Block Diagram
HYM 324020S/GS-60/-70
4M x 32-Bit
Semiconductor Group
575
HYM 324020S/GS-60/-70
4M x 32-Bit
Absolute Maximum Ratings
Operation temperature range ......................................................................................... 0 to + 70 C
Storage temperature range......................................................................................... 55 to 125 C
Soldering temperature ............................................................................................................ 260 C
Soldering time ............................................................................................................................. 10 s
Input/output voltage ........................................................................ 0.5 V to min (
V
CC
+ 0.5, 7.0) V
Power supply voltage...................................................................................................... 1 to + 7 V
Power dissipation................................................................................................................... 6.16 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
DC Characteristics
1)
T
A
= 0 to 70 C,
V
CC
= 5 V
10 %
Parameter
Symbol
Limit Values
Unit
Test
Condition
min.
max.
Input high voltage
V
IH
2.4
V
CC
+ 0.5
V
Input low voltage
V
IL
0.5
0.8
V
Output high voltage (
I
OUT
= 5 mA)
V
OH
2.4
V
Output low voltage (
I
OUT
= 4.2 mA)
V
OL
0.4
V
Input leakage current
(0 V <
V
IN
< 6.5 V, all other pins = 0 V)
I
I(L)
20
20
A
Output leakage current
(DO is disabled, 0 V <
V
OUT
< 5.5 V)
I
O(L)
10
10
A
Average
V
CC
supply current
(RAS, CAS, address cycling,
t
RC
=
t
RC
min)
60 ns - Version
70 ns - Version
I
CC1
880
800
mA
mA
2)
3)
Standby
V
CC
supply current
(RAS = CAS =
V
IH
)
I
CC2
16
mA
Average
V
CC
supply current
during RAS only refresh cycles
(RAS cycling, CAS =
V
IH
,
t
RC
=
t
RC
min)
60 ns - Version
70 ns - Version
I
CC3
880
800
mA
mA
2)
Semiconductor Group
576
DC Characteristics
1)
(cont'd)
Capacitance
T
A
= 0 to 70 C,
V
CC
= 5 V
10 %,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
Test
Condition
min.
max.
Average
V
CC
supply current
during fast page mode
(RAS =
V
IL
, CAS, address cycling,
t
PC
=
t
PC
min)
60 ns - Version
70 ns - Version
I
CC4
640
560
mA
mA
2)
3)
Standby
V
CC
supply current
(RAS = CAS =
V
CC
0.2 V)
I
CC5
8
mA
Average
V
CC
supply current
during CAS-before-RAS refresh mode
(RAS, CAS cycling,
t
RC
=
t
RC
min)
60 ns - Version
70 ns - Version
I
CC6
880
800
mA
mA
2)
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A10,WE)
C
I1
90
pF
Input capacitance (RAS0, RAS2)
C
I2
45
pF
Input capacitance (CAS0 - CAS3)
C
I3
40
pF
I/O capacitance
(DQ0-DQ31)
C
IO
25
pF
HYM 324020S/GS-60/-70
4M x 32-Bit
Semiconductor Group
577
AC Characteristics
4) 5)
T
A
= 0 to 70 C,
V
CC
= 5 V
10 %,
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit
HYM
324020S/GS-60
HYM
324020S/GS-70
min.
max.
min.
max.
Random read or write cycle time
t
RC
110
130
ns
Fast page mode cycle time
t
PC
40
45
ns
Access time from RAS
6) 11) 12)
t
RAC
60
70
ns
Access time from CAS
6) 11)
t
CAC
15
20
ns
Access time from column
address
6) 12)
t
AA
30
35
ns
Access time from CAS
precharge
6)
t
CPA
35
40
ns
CAS to output in low-Z
6)
t
CLZ
0
0
ns
Output buffer turn-off delay
7)
t
OFF
0
20
0
20
ns
Transition time (rise and fall)
5)
t
T
3
50
3
50
ns
RAS precharge time
t
RP
40
50
ns
RAS pulse width
t
RAS
60
10000
70
10000
ns
RAS pulse width
(fast page mode)
t
RASP
60
200000
70
200000
ns
CAS precharge to RAS delay
t
RHCP
35
40
ns
RAS hold time
t
RSH
15
20
ns
CAS hold time
t
CSH
60
70
ns
CAS pulse width
t
CAS
15
10000
20
10000
ns
RAS to CAS delay time
11)
t
RCD
20
45
20
50
ns
RAS to column address
delay time
12)
t
RAD
15
30
15
35
ns
CAS to RAS precharge time
t
CRP
5
5
ns
CAS precharge time
(fast page mode)
t
CP
10
10
ns
Row address setup time
t
ASR
0
0
ns
Row address hold time
t
RAH
10
10
ns
Column address setup time
t
ASC
0
0
ns
Column address hold time
t
CAH
15
15
ns
HYM 324020S/GS-60/-70
4M x 32-Bit
Semiconductor Group
578
AC Characteristics
4) 5)
(cont'd)
T
A
= 0 to 70 C,
V
CC
= 5 V
10 %,
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit
HYM
324020S/GS-60
HYM
324020S/GS-70
min.
max.
min.
max.
Column address to RAS lead time
t
RAL
30
35
ns
Read command setup time
t
RCS
0
0
ns
Read command hold time
8)
t
RCH
0
0
ns
Read command hold time
ref. to RAS
8)
t
RRH
0
0
ns
Write command hold time
t
WCH
10
15
ns
Write command pulse width
t
WP
10
15
ns
Write command to RAS lead time
t
RWL
15
20
ns
Write command to CAS lead time
t
CWL
15
20
ns
Data setup time
9)
t
DS
0
0
ns
Data hold time
9)
t
DH
15
15
ns
Refresh period
t
REF
32
32
ms
Write command setup time
10)
t
WCS
0
0
ns
CAS setup time
13)
t
CSR
10
10
ns
CAS hold time
13)
t
CHR
10
10
ns
RAS to CAS precharge time
t
RPC
5
5
ns
CAS precharge time
t
CP
10
10
ns
Write to RAS precharge time
13)
t
WRP
10
10
ns
Write hold time ref. to RAS
13)
t
WRH
10
10
ns
HYM 324020S/GS-60/-70
4M x 32-Bit
Semiconductor Group
579
Notes
1) All voltages are referenced to
V
SS
.
2)
I
CC1
,
I
CC3
,
I
CC4
and
I
CC6
depend on cycle rate.
3)
I
CC1
and
I
CC4
depend on output loading.
Specified values are measured with the output open.
4) An initial pause of 200
s is required after power-up followed by 8 RAS cycles out of which at least one cycle
has to be a refresh cycle before proper device operation is achieved. In case of using internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
5)
V
IH
(max)
and
V
IL
(max)
are reference levels for measuring timing of input signals.
Transition times are also measured between
V
IH
and
V
IL
.
6) Measured with a load equivalent of 2 TTL loads and 100 pF.
7)
t
OFF
(max)
defines the time at which the output achieves the open-circuit condition and is not referenced to
output voltage levels.
8) Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
9) These parameters are referenced to the CAS leading edge.
10)
t
WCS
is not a restrictive operating parameter. This is included in the data sheet as electrical characteristic only.
If
t
WCS
>
t
WCS
(min)
, the cycle is an early write cycle and data out pin will remain open (high impedance).
11) Operation within the
t
RCD
(max)
limit insures that
t
RAC
(max)
can be met.
t
RCD
(max)
is specified as a reference point
only. If
t
RCD
is greater than the specified
t
RCD
(max)
limit, then access time is controlled by
t
CAS
.
12) Operation within the
t
RAD
(max)
limit insures that
t
RAC
(max)
can be met.
t
RAD
(max)
is specified as a reference point
only. If
t
RAD
is greater than the specified
t
RAD
(max)
limit, then access time is controlled by
t
AA
.
13) For CAS-before-RAS cycles only.
HYM 324020S/GS-60/-70
4M x 32-Bit
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