Semiconductor Group
1
8M x 36-Bit EDO - DRAM Module
HYM 368025S/GS-50/-60
SIMM modules with 8 388 608 words by 36-bit organization in two banks
for PC main memory applications
Fast access and cycle time
50 ns access time
84 ns cycle time (-50 version)
60 ns access time
104 ns cycle time (-60 version)
Hyper Page Mode (EDO) capability
20 ns cycle time (-50 version)
25 ns cycle time (-60 version)
Single + 5 V (
10 %) supply
Low power dissipation
max. 6820 mW active (-50 version)
max. 6160 mW active (-60 version)
CMOS 132 mW standby
TTL
264 mW standby
CAS-before-RAS refresh
RAS-only-refresh
Hidden-refresh
Decoupling capacitors mounted on substrate
All inputs, outputs and clocks fully TTL compatible
72 pin Single in-Line Memory Module (L-SIM-72-14) with 31.75 mm height
Utilizes sixteen 4Mx4-EDO-DRAMs and eight 4M x 1 EDO-DRAMs
in 300 mil wide SOJ packages
2048 refresh cycles / 32 ms
Optimized for use in byte-write parity applications
Tin-Lead contact pads (S- version)
Gold contact pads (GS - version)
4.97
Semiconductor Group
2
HYM 368025S/GS-50/-60
8M
36-Bit EDO-Module
The HYM 368025S/GS-50/-60 is a 32 MByte DRAM module organized as 8 388 608 words by 36-
Bit in two banks in a 72-pin single-in-line package comprising sixteen HYB 5117405BJ 4M
4
EDO-DRAMs and eight HYB 514105BJ 4M x 1 EDO-DRAMs in 300 mil wide SOJ-packages
mounted together with decoupling capacitors on a PC board.
Each HYB 5117405BJ and HYB 514105BJ is described in the data sheet and is fully electrical
tested and processed according to SIEMENS standard quality procedure prior to module assembly.
After assembly onto the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 368025S/GS-50/-60 dictates the use of early write cycles.
Ordering Information
Type
Ordering Code
Package
Description
HYM 368025S-50
L-SIM-72-14
EDO-DRAM Module
(access time 50 ns)
HYM 368025S-60
L-SIM-72-14
EDO-DRAM Module
(access time 60 ns)
HYM 368025GS-50
L-SIM-72-14
EDO-DRAM Module
(access time 50 ns)
HYM 368025GS-60
L-SIM-72-14
EDO-DRAM Module
(access time 60 ns)
Semiconductor Group
3
HYM 368025S/GS-50/-60
8M
36-Bit EDO-Module
Pin Configuration
Pin Names
Presence Detect Pins
A0-A10
Address Inputs
DQ0-DQ35
Data Input/Output
CAS0 - CAS3
Column Address Strobe
RAS0- RAS3
Row Address Strobe
WE
Read/Write Input
V
CC
Power (+ 5 V)
V
SS
Ground
PD
Presence Detect Pin
N.C.
No Connection
-50
-60
PD0
N.C.
N.C.
PD1
V
SS
V
SS
PD2
V
SS
N.C.
PD3
V
SS
N.C.
VSS 1 DQ0 2
DQ18 3 DQ1 4
DQ19 5 DQ2 6
DQ20 7 DQ3 8
DQ21 9 VCC 10
N.C. 11 A0 12
A1 13 A2 14
A3 15 A4 16
A5 17 A6 18
A10 19 DQ4 20
DQ22 21 DQ5 22
DQ23 23 DQ6 24
DQ24 25 DQ7 26
DQ25 27 A7 28
N.C. 29 VCC 30
A8 31 A9 32
RAS3 33 RAS2 34
DQ26 35 DQ8 36
DQ17 37 DQ35 38
VSS 39 CAS0 40
CAS2 41 CAS3 42
CAS1 43 RAS0 44
RAS1 45 N.C. 46
WE 47 N.C. 48
DQ9 49 DQ27 50
DQ10 51 DQ28 52
DQ11 53 DQ29 54
DQ12 55 DQ30 56
DQ13 57 DQ31 58
VCC 59 DQ32 60
DQ14 61 DQ33 62
DQ15 63 DQ34 64
DQ16 65 N.C. 66
PD0 67 PD1 68
PD2 69 PD3 70
N.C. 71 VSS 72
Semiconductor Group
4
HYM 368025S/GS-50/-60
8M
36-Bit EDO-Module
Block Diagram
CAS RAS
I/O1-I/O4
OE
CAS RAS
Di
Do
CAS RAS
I/O1-I/O4
OE
CAS RAS
Di
Do
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
Di
Do
CAS RAS
I/O1-I/O4
OE
CAS RAS
Di
Do
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
Di
Do
CAS RAS
I/O1-I/O4
OE
CAS RAS
Di
Do
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
CAS RAS
Di
Do
CAS RAS
I/O1-I/O4
OE
CAS RAS
Di
Do
CAS RAS
I/O1-I/O4
OE
CAS RAS
I/O1-I/O4
OE
RAS0
CAS0
DQ0-DQ3
DQ4-DQ7
DQ8
CAS1
DQ9-DQ12
DQ13-DQ16
DQ17
RAS2
CAS2
DQ18-DQ21
DQ22-DQ25
DQ26
CAS3
DQ27-DQ30
DQ31-DQ34
DQ35
RAS1
RAS3
D0
D3
M0
D4
D7
M2
D8
D11
M4
D12
D15
M6
D0-D15, M0-M7
D0-D15, M0-M7
A0-A10
WE
C0 - C23
VCC
VSS
D1
D2
M1
D5
D6
M3
D9
D10
M5
D13
D14
M7
Semiconductor Group
5
HYM 368025S/GS-50/-60
8M
36-Bit EDO-Module
Absolute Maximum Ratings
Operation temperature range .........................................................................................
0 to + 70 C
Storage temperature range.........................................................................................
55 to 125 C
Input/output voltage ............................................................................ 0.5V to min (Vcc+0.5, 7.0) V
Power supply voltage......................................................................................................
1 to + 7 V
Power dissipation...................................................................................................................
9.24 W
Data out current (short circuit) ................................................................................................
50 mA
Note:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
T
A
= 0 to 70 C,
V
CC
= 5 V
10 %
Parameter
Symbol
Limit Values
Unit
Test
Condition
min.
max.
Input high voltage
V
IH
2.4
Vcc+0.5
V
1)
Input low voltage
V
IL
0.5
0.8
V
1)
Output high voltage (
I
OUT
= 5 mA)
V
OH
2.4
V
1)
Output low voltage (
I
OUT
= 4.2 mA)
V
OL
0.4
V
1)
Input leakage current
(0 V <
V
IN
< 6.5 V, all other pins = 0 V)
I
I(L)
20
20
A
1)
Output leakage current
(DO is disabled, 0 V <
V
OUT
< 5.5 V)
I
O(L)
20
20
A
1)
Average
V
CC
supply current
(RAS, CAS, address cycling,
t
RC
=
t
RC
min)
-50 version
-60 version
I
CC1
1240
1120
mA
mA
2),3),4)
Standby
V
CC
supply current
(RAS = CAS =
V
IH
)
I
CC2
48
mA
Average
V
CC
supply current
during RAS only refresh cycles (per bank)
(RAS cycling, CAS =
V
IH
,
t
RC
=
t
RC
min)
-50 version
-60 version
I
CC3
1240
1120
mA
mA
2),4)
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