Semiconductor Group
1
1M
64-Bit Dynamic RAM Module
HYM 641010GS-60/-70
HYM 641020GS-60/-70
Advanced Information
1 048 576 words by 64-bit organization
Fast access and cycle time
60 ns access time
110 ns cycle time (-60 version)
70 ns access time
130 ns cycle time (-70 version)
Fast page mode capability with
40 ns cycle time (-60 version)
45 ns cycle time (-70 version)
Single + 5 V (
10 %) supply
Low power dissipation
max. 9680 mW active (-60 version)
max. 8800 mW active (-70 version)
CMOS 451
mW
standby
TTL
550 mW standby
CAS-before-RAS refresh, RAS-only-refresh
Byte Write Capability
16 decoupling capacitors mounted on substrate
All inputs, outputs and clock fully TTL compatible
4 Byte interleave enabled, Dual Address inputs (A0/B0)
Buffered inputs except RAS and DQ
168 pin, dual read-out, Single in-Line Memory Module
Utilizes sixteen 1M
4 -DRAMs (HYB 514400BJ/BT) and
four BiCMOS 8-bit buffers/line drivers 74ABT244
Two version : HYM 641010GS with SOJ-components (8.89 mm module thickness)
HYM 641020GS with TSOPII-components (4.06 mm module thickness)
1024 refresh cycles / 16 ms
Optimized for use in byte-write non-parity applications
Gold contact pads,double sided module with 25.35 mm (1000 mil) height
1
12.95
Semiconductor Group
2
HYM 641010/20GS-60/-70
1M x 64 Module
The HYM 641010/20GS-60/-70 is a 8 MByte DRAM module organized as 1 048 576 words by 64-
bit in a 168-pin, dual read-out, single-in-line package comprising sixteen HYB 514400BJ/BT 1M
4 DRAMs in 300 mil wide SOJ or TSOPII - packages mounted together with sixteen 0.2
F
ceramic decoupling capacitors on a PC board. All inputs except RAS and DQ are buffered by using
four BiCMOS 8-bit buffers/line drivers.
Each HYB 514400BJ/BT is described in the data sheet and is fully electrically tested and processed
according to Siemens standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.
The density and speed of the module can be detected by the use of presence detect pins.
Ordering Information
Pin Names
Presence-Detect and ID-pin Truth Table:
Note: 1 = high level ( driver output), 0 = low level ( driver output) for PDE active ( ground) . For PDE at a high level
all PD terminals are in tri-state.
Type
Ordering Code
Package
Descriptions
HYM 641020GS-60
Q67100 - Q2003
L-DIM-168-1
60 ns DRAM module
HYM 641020GS-70
on request
L-DIM-168-1
70 ns DRAM module
HYM 641010GS-60
Q67100 - Q2002
L-DIM-168-1
60 ns DRAM module
HYM 641010GS-70
on request
L-DIM-168-1
70 ns DRAM module
A0-A9,B0
Address Input
DQ0 - DQ63
Data Input/Output
RAS0, RAS2
Row Address Strobe
CAS0 - CAS7
Column Address Strobe
WE0, WE2
Read / Write Input
OE0, OE2
Output Enable
Vcc
Power (+5 Volt)
Vss
Ground
PD1 - PD8
Presence Detect Pins
PDE
Presence Detect Enable
ID0 , ID1
ID indentification bit
N.C.
No Connection
Module
ID0
ID1
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
HYM 641010/20GS-60
Vss
Vss
0
0
1
0
0
1
1
1
HYM 641010/20GS-70
Vss
Vss
0
0
1
0
0
0
1
1
Semiconductor Group
3
HYM 641010/20GS-60/-70
1M x 64 Module
Pin Configuration
PIN #
Symbol
PIN #
Symbol
PIN #
Symbol
PIN #
Symbol
1
VSS
43
VSS
85
VSS
127
VSS
2
DQ0
44
OE2
86
DQ32
128
NC
3
DQ1
45
RAS2
87
DQ33
129
NC
4
DQ2
46
CAS4
88
DQ34
130
CAS5
5
DQ3
47
CAS6
89
DQ35
131
CAS7
6
VCC
48
WE2
90
VCC
132
PDE
7
DQ4
49
VCC
91
DQ36
133
VCC
8
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
DQ16
94
DQ39
136
DQ48
11
NC
53
DQ17
95
NC
137
DQ49
12
VSS
54
VSS
96
VSS
138
VSS
13
DQ8
55
DQ18
97
DQ40
139
DQ50
14
DQ9
56
DQ19
98
DQ41
140
DQ51
15
DQ10
57
DQ20
99
DQ42
141
DQ52
16
DQ11
58
DQ21
100
DQ43
142
DQ53
17
DQ12
59
VCC
101
DQ44
143
VCC
18
VCC
60
DQ22
102
VCC
144
DQ54
19
DQ13
61
NC
103
DQ45
145
NC
20
DQ14
62
NC
104
DQ46
146
NC
21
DQ15
63
NC
105
DQ47
147
NC
22
NC
64
NC
106
NC
148
NC
23
VSS
65
DQ23
107
VSS
149
DQ55
24
NC
66
NC
108
NC
150
NC
25
NC
67
DQ24
109
NC
151
DQ55
26
VCC
68
VSS
110
VCC
152
VSS
27
WE0
69
DQ25
111
NC
153
DQ57
28
CAS0
70
DQ26
112
CAS1
154
DQ58
29
CAS2
71
DQ27
113
CAS3
155
DQ59
30
RAS0
72
DQ28
114
NC
156
DQ60
31
OE0
73
VCC
115
NC
157
VCC
32
VSS
74
DQ29
116
VSS
158
DQ61
33
A0
75
DQ30
117
A1
159
DQ62
34
A2
76
DQ31
118
A3
160
DQ63
35
A4
77
NC
119
A5
161
NC
36
A6
78
VSS
120
A7
162
VSS
37
A8
79
PD1
121
A9
163
PD2
38
NC
80
PD3
122
NC
164
PD4
39
NC
81
PD5
123
NC
165
PD6
40
VCC
82
PD7
124
VCC
166
PD8
41
NC
83
ID0
125
NC
167
ID1
42
NC
84
VCC
126
B0
168
VCC
Semiconductor Group
4
HYM 641010/20GS-60/-70
1M x 64 Module
Block Diagram
I/O1-I/O4
D0
I/O1-I/O4
D1
I/O1-I/O4
D2
I/O1-I/O4
D3
I/O1-I/O4
D4
I/O1-I/O4
D5
I/O1-I/O4
D6
I/O1-I/O4
D7
I/O1-I/O4
D8
I/O1-I/O4
D9
I/O1-I/O4
D10
I/O1-I/O4
D11
I/O1-I/O4
D12
I/O1-I/O4
D13
I/O1-I/O4
D14
I/O1-I/O4
D15
D0 - D7
D8 - D15
D0 - D17
DQ0-DQ3
DQ4-DQ7
RAS0
CAS0
WE0
OE0
DQ8-DQ11
DQ12-DQ15
DQ16-DQ19
DQ20-DQ23
DQ24-DQ27
DQ28-DQ31
DQ32-DQ35
DQ36-DQ39
DQ40-DQ43
DQ44-DQ47
DQ48-DQ51
DQ52-DQ55
DQ56-DQ59
DQ60-DQ63
A0
B0
A1-A9
Vcc
Vss
D0-D15, buffers
RAS2
CAS4
WE2
OE2
CAS5
CAS1
CAS2
CAS6
CAS3
CAS7
Semiconductor Group
5
HYM 641010/20GS-60/-70
1M x 64 Module
Absolute Maximum Ratings
Operating temperature range ......................................................................................... 0 to + 70 C
Storage temperature range...................................................................................... 55 to + 125 C
Input/output voltage ........................................................................................................ 1 to + 7 V
Power supply voltage...................................................................................................... 1 to + 7 V
Power dissipation................................................................................................................ 12,32 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
1)
T
A
= 0 to 70 C;
V
CC
= 5 V
10 %
Parameter
Symbol
Limit Values
Unit
Test
Condition
min.
max.
Input high voltage
V
IH
2.4
5.5
V
Input low voltage
V
IL
1.0
0.8
V
Output high voltage (
I
OUT
= 5 mA)
V
OH
2.4
V
Output low voltage (
I
OUT
= 4.2 mA)
V
OL
0.4
V
Input leakage current
(0 V <
V
IN
< 6.5 V, all other pins = 0 V)
I
I(L)
10
10
A
Output leakage current
(DO is disabled, 0 V <
V
OUT
< 5.5 V)
I
O(L)
10
10
A
Average
V
CC
supply current:
HYM 641010/20GS-60
HYM 641010/20GS-70
(RAS, CAS, address cycling,
t
RC
=
t
RC
min.)
I
CC1
1760
1600
mA
mA
2), 3)
Standby
V
CC
supply current
(RAS = CAS =
V
IH
)
I
CC2
50
mA
Average
V
CC
supply current during RAS
only refresh cycles:
HYM 641010/20GS-60
HYM 641010/20GS-70
(RAS cycling, CAS =
V
IH
, t
RC
=
t
RC
min.)
I
CC3
1760
1600
mA
mA
2)
Semiconductor Group
6
HYM 641010/20GS-60/-70
1M x 64 Module
DC Characteristics (cont'd)
1)
Capacitance
T
A
= 0 to 70 C;
V
CC
= 5 V
10 %;
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
Test
Condition
min.
max.
Average
V
CC
supply current during fast
page mode:
HYM 641010/20GS-60
HYM 641010/20GS-70
(RAS =
V
IL,
CAS, address cycling
t
PC
=
t
PC
min.)
I
CC4
1120
1120
mA
mA
2), 3)
Standby
V
CC
supply current
(RAS = CAS =
V
CC
0.2 V)
I
CC5
30
mA
Average
V
CC
supply current during
CAS-before-RAS refresh mode:
HYM 641010/20GS-60
HYM 641010/20GS-70
(RAS, CAS cycling
, t
RC
=
t
RC
min.)
I
CC6
1760
1600
mA
mA
1)
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A9,B0)
C
I1
10
pF
Input capacitance (RAS0, RAS2)
C
I2
50
pF
Input capacitance (CAS0-CAS7)
C
I3
15
pF
Input capacitance (WE0,WE2,OE0,OE2)
C
I4
15
pF
I/O capacitance (DQ0-DQ63)
C
IO1
15
pF
Semiconductor Group
7
HYM 641010/20GS-60/-70
1M x 64 Module
AC Characteristics (note: 5,6,7,8)
T
A
= 0 to 70 C,
V
CC
= 5.0
10 %
Parameter
Symbol
-60
-70
Unit
Note
min.
max.
min.
max.
common parameters
Random read or write cycle time
t
RC
110
130
ns
RAS precharge time
t
RP
40
50
ns
RAS pulse width
t
RAS
60
100k
70
100k
ns
CAS pulse width
t
CAS
15
100k
20
100k
ns
CAS precharge time
t
CP
10
10
ns
Row address setup time
t
ASR
5
5
ns
9
Row address hold time
t
RAH
8
8
ns
10
Column address setup time
t
ASC
2
2
ns
11
Column address hold time
t
CAH
15
20
ns
9
RAS to CAS delay time
t
RCD
18
40
18
45
12
RAS to column address delay time
t
RAD
13
25
13
30
ns
12
RAS hold time
t
RSH
20
25
ns
9
CAS hold time
t
CSH
58
68
ns
10
CAS to RAS precharge time
t
CRP
10
10
ns
9
Transition time (rise and fall)
t
T
3
30
3
30
ns
7
Refresh period
t
REF
16
16
ms
Read Cycle
Access time from RAS
t
RAC
60
70
ns
13,14
Access time from CAS
t
CAC
20
25
ns
9,13,14
Access time from column address
t
AA
35
40
ns
9,13, 15
OE access time
t
OEA
20
25
ns
9,13
Column address to RAS lead time
t
RAL
35
40
ns
9
Read command setup time
t
RCS
2
2
ns
11
Read command hold time
t
RCH
2
2
ns
11,16
Read command hold time referenced
to RAS
t
RRH
0
0
ns
16
CAS to output in low-Z
t
CLZ
2
2
ns
11,13
Output buffer turn-off delay
t
OFF
20
25
ns
9,17
Output buffer turn-off delay from OE
t
OEZ
20
25
ns
9,17
Semiconductor Group
8
HYM 641010/20GS-60/-70
1M x 64 Module
CAS delay time from Din
t
DZC
0
0
ns
18
Data to OE low delay
t
DZO
0
0
ns
18
CAS high to data delay
t
CDD
20
25
ns
9,19
OE high to data delay
t
ODD
20
25
ns
9,19
Write Cycle
Write command hold time
t
WCH
15
15
ns
9
Write command pulse width
t
WP
10
10
ns
Write command setup time
t
WCS
2
2
ns
11,20
Write command to RAS lead time
t
RWL
20
25
ns
9
Write command to CAS lead time
t
CWL
15
20
ns
Data setup time
t
DS
-2
-2
ns
10,21
Data hold time
t
DH
15
20
ns
9,21
Read-Modify-Write Cycle
Read-write cycle time
t
RWC
155
185
ns
9
RAS to WE delay time
t
RWD
82
97
ns
11,21
CAS to WE delay time
t
CWD
37
47
ns
11,21
Column address to WE delay time
t
AWD
52
62
ns
11,21
OE command hold time
t
OEH
13
18
ns
10
Fast Page Mode Cycle
Fast page mode cycle time
t
PC
40
45
ns
Access time from CAS precharge
t
CPA
40
45
ns
9,13
RAS pulse width
t
RAS
60
200k
70
200k
ns
CAS precharge to RAS Delay
t
RHCP
40
45
ns
9
AC Characteristics (cont'd)(note: 5,6,7,8)
T
A
= 0 to 70 C,
V
CC
= 5.0
10 %
Parameter
Symbol
-60
-70
Unit
Note
min.
max.
min.
max.
Semiconductor Group
9
HYM 641010/20GS-60/-70
1M x 64 Module
Fast Page Mode Read-Modify-Write
Cycle
Fast page mode read-write cycle time
t
PRWC
82
97
ns
11
CAS precharge to WE
t
CPWD
57
67
ns
11,21
CAS-before-RAS Refresh Cycle
CAS setup time
t
CSR
12
12
ns
11
CAS hold time
t
CHR
8
8
ns
10
RAS to CAS precharge time
t
RPC
5
5
ns
Write to RAS precharge time
t
WRP
12
12
ns
11
Write hold time referenced to RAS
t
WRH
8
8
ns
10
Presence Detect Read Cycle
PDE to valid presence detect data
t
PD
10
ns
PDE inactive to presence detects
inactive
t
PDOFF
0
10
ns
AC Characteristics (cont'd)(note: 5,6,7,8)
T
A
= 0 to 70 C,
V
CC
= 5.0
10 %
Parameter
Symbol
-60
-70
Unit
Note
min.
max.
min.
max.
Semiconductor Group
10
HYM 641010/20GS-60/-70
1M x 64 Module
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less
during a fast page mode cycle ( tpc).
5) An initial pause of 100
s is required after power-up followed by 8 RAS-only-refresh cycles, before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS
initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are
measured between VIH and VIL.
8) The specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns (CAS, WE, OE,
addresses) maximum delay, no pulse shrinkage to the DRAM device timings. The data and RAS signals are
not buffered, which preserves the DRAMs access specification of 50ns and 60ns.
9) A +5ns timing skew from the DRAM to the module resulted from the addition of line drivers.
10) A -2ns timing skew from the DRAM to the module resulted from the addition of line drivers.
11) A +2ns timing skew from the DRAM to the module resulted from the addition of line drivers.
12) A -2ns (min.) and a -5ns (max.) timing skew from the DRAM to the module resulted from the addition of line
drivers.
13) Measured with the specified current load and 100 pF at Voh = 2.4 V and Vol = 0.4 V.
14) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
15) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
16) Either tRCH or tRRH must be satisfied for a read cycle.
17) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
not referenced to output voltage levels.
18) Either tDZC or tDZO must be satisfied.
19) Either tCDD or tODD must be satisfied.
20) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition
of the I/O pins (at access time) is indeterminate.
21) These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in Read-
Modify-Write cycles.
Semiconductor Group
11
HYM 641010/20GS-60/-70
1M x 64 Module
L-DIM-168-1
(dual read-out, single in-line memory module)
Module package
GLD05860
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