Functional Description

Multistandard sound IF-device consisting of a mixer as a frequency converter, a voltage-controlled
oscillator (VCO) that can be continuously tuned in 10-kHz increments with crystal accuracy by
means of a PLL, and three following parallel FM-limiter amplifiers with coincidence demodulators.

The switching functions and setting of the PLL are controlled on an

C bus.

Application

For use in satellite receivers.

Type

Ordering Code

Package

TDA 6160-2X

Q67000-A5085

P-DSO-28-1 (SMD)

Multistandard Sound IF

Preliminary Data

Bipolar IC

TDA 6160-2X

P-DSO-28-1

Features

Sound carrier mixer

VCO

Programmable Divider

Reference divider with crystal oscillator

Phase comparator

Operational amplifier for PLL filter

C bus interface

3 identical FM channels with limiter amplifiers
and coincidence demodulators.

Semiconductor Group

143

08.93

Semiconductor Group

144

Pin Functions

Pin No.

Function

Quartz oscillator

PD-output / integrator input (

REF

)

Integrator output (

)

VCO

Chip address switching (CA)

Demodulator circuit (IF-1)

AF-output 1

Demodulator circuit (IF-2)

AF-output 2

Demodulator circuit (IF-3)

AF-output 3

IF-input 3

(analog)

IF-input 2

Ground (analog)

IF-input 1

IF-reference

Mixer output 2

Mixer output 1

Mixer input (reference)

Mixer input

Ground (digital)

(digital)

C bus (SCL)

C bus (SDA)

TDA 6160-2X

Semiconductor Group

150

Circuit Description

The sound intermediate frequencies contained in the baseband of a demodulated FM satellite
signal can lie between 5 and 9 MHz. This band of frequencies is applied ready filtered to the input
of the converter mixer. The purpose of this mixer is to convert the different sound IFs in the
baseband to fixed output frequencies (e.g. 10.7/10.52 MHz). These frequencies are then fed by
external filters to the inputs of the three sound IF-amplifiers.

The VCO of the mixer can be continuously tuned between 14.5 and 20 MHz in 10-kHz increments
with crystal accuracy by means of a PLL-circuit.

The setting of the programmable divider and the cutting in and out of the sound IF-amplifiers are
controlled on the

C bus.

Pin 5 (CA) offers two switchable chip addresses to enable parallel operation of two devices.

All pins are guarded against electrostatic discharge. SCL and SDA include special protective
structures to permit continued bus operation when the device is switched off.

PLL

The VCO-signal, DC coupled internally, is applied to the PLL-input. It passes through a
programmable divider (

= 1024 to 2047) and is then compared to a reference frequency

(

REF

= 10 kHz) in a digital frequency/phase detector. This frequency is derived from a 4-MHz crystal

oscillator whose signal is divided by 400.

The phase detector has a charge-pump push-pull current output. If the negative edge of the divided
VCO-signal appears before the negative edge of the reference signal, the current source

+ will

pulse for the duration of the phase difference. In the reverse case it is the current sink

�. If both

signals are in-phase, the output is high-impedance and the PLL is locked in. The current pulses are
filtered by means of an integrator (internal operational amplifier with external RC-circuitry).

The pump current can be switched between the two values 1 and 5 by software with a control bit 5I.
This permits a change in the control response during and after the lock-in state.

C Bus Interface

Information is exchanged between the processor and the sound IF-device on an asynchronous
bidirectional data bus. The timing for this comes from the processor (input SCL), while pin SDA-
functions as an input or output depending on the direction of the data (open collector; external
pull-up resistor).

The data from the processor go to an

C bus controller and are filed in registers (latches 0 to 2)

according to their function. When the bus is not busy, both lines are in marking state (SDA, SCL are
high). Each telegram begins with the start condition: SDA goes low while SCL remains high. All
further exchanges of information are while SCL is low and are read by the controller with the positive
clock edge. If SDA goes high while the clock is high, the PLL recognizes this as a stop condition and
thus the end of the telegram.

For what follows, refer to the table of logic assignments below.

All telegrams are transferred byte by byte, followed by a ninth clock pulse during which the controller
pulls the SDA-line to low (i.e. acknowledge condition). The first byte consists of seven address bits
with which the processor selects the PLL from among several peripheral devices (chip select). The

TDA 6160-2X

Semiconductor Group

151

TDA 6160-2X

eighth bit is always low. The first bit of the first or third data byte in the data part of the telegram
determines whether a divider ratio or control information will follow. In every case the first byte must
be followed by a byte of the same data type (or a stop condition). When the supply voltage is
applied, a power-on reset circuit prevents the PLL from pulling the SDA-line to low and thus blocking
the bus.

Logic Allocations

Chip address (CA)
pin 5 on:

ground

= address byte 1

or open = address byte 2

Test Mode

T2, T1, T0 = 0, 0, 0

normal operation

T2, T1, T0 = 1, 0, 0

pin 2

REF

T2, T1, T0 = 1, 1, 0

pin 2

T2, T1, T0 = 1, 1, 1

pin 2

= tristate

T2, T1, T0 = 0, 1, 1

pin 2

= high-impedance = pin 3 high-impedance

IF-Muting Circuits

Z2, Z1, Z0 = 0, 0, 0

normal operation

Z2, Z1, Z0 = 0, 0, 1

IF 3

= off (output 14 high-impedance)

Z2, Z1, Z0 = 0, 1, 0

IF 2

= off (output 11 high-impedance)

Z2, Z1, Z0 = 0, 1, 1

IF 1 = on; IF 2/IF 3 = off

Z2, Z1, Z0 = 1, 0, 0

IF 1

= off (output 8 high-impedance)

Z2, Z1, Z0 = 1, 0, 1

IF 1 = off; IF 2 = on; IF 3 = off

Z2, Z1, Z0 = 1, 1, 0

IF 3 = on; IF 1/IF 2 = off

Z2, Z1, Z0 = 1, 1, 1

IF 1, IF 2, IF 3 = off

Address byte

Progr. divider byte 1

MA1

MA0

R/W

n10

Progr. divider byte 2

Control information

Address byte 1

Address byte 2

= H46

= H44

Semiconductor Group

152

Telegram Examples

Start-AB-DB1-DB2-CI-Stop

Start = start condition
AB

= address byte

Start-AB-CI-DB1-DB2-Stop

DB1 = divider byte 1

Start-AB-DB1-Stop

DB2 = divider byte 2
CI

= control information

Start-AB-CI-Stop

Stop = stop condition

Converter Mixer + VCO
In the converter mixer the sound subcarriers (frequency band approx. 5 to 9 MHz) contained in the
baseband of the received composite signal are converted to an output frequency of 10.52 MHz or
10.7 MHz for example. The two mixer outputs are designed as open-collector outputs.

The VCO has internal feedback and its frequency of 15.5 to 19.7 MHz is determined by an external
resonant circuit with a varactor diode that is tuned by the PLL. The resonant circuit is connected to
the supply voltage by its low side.

IF-Limiter with Demodulators

The limiter amplifiers are implemented as balanced five-stage, capacitively coupled differential
amplifiers. All there limiter inputs have a common reference (pin 20).

The output signals of the limiter amplifiers are fed direct and via an external phase-shifter circuit to
the coincidence demodulators. The AF-signals can be brought out an disconnectible (by Z2, Z1, Z0)
AF output stages. The outputs are high-impedance when they are disconnected.

TDA 6160-2X

Semiconductor Group

153

TDA 6160-2X

Absolute Maximum Ratings

= 0 to 70

�

Parameter

Symbol

Limit Values

Unit

min.

max.

Supply voltage

AF-output

� 1.5

AF-output

Demodulators

6/7

9/10

12/13

IF-inputs

Mixer outputs

VCO

Crystal oscillator

1.5

Junction temperature

150

�

Storage temperature

stg

125

�

Thermal resistance

th SA

K/W

All voltage values are referred to ground (pin 18, pin 25), unless stated otherwise.
All currents are designated according to the source and sink principle, i.e. if the device pin is to be
regarded as a sink (the current flows into the stated pin to internal ground), it has a negative sign,
and if it is a source (the current flows from

across the designated pin), it has a positive sign.

Operating Range

Supply voltage

4.5

5.5

Input frequency range
of converter mixer

I24

MHz

Input frequency range of sound
IF-amplifiers (� 3 dB)

I15, 17, 19

MHz

VCO-frequency

MHz

Ambient temperature

�

Semiconductor Group

154

Characteristics

= 5 V;

= 25

�

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

Current drain (analog section)

Current drain (digital section)

Phase-detector
charge current

�

160

�

250

�

360

�

I
5I

Mixer

Static Characteristics

Mixer output currents

21, 22

1.1

3.5

Output-current difference

�

100

�

Mixer inputs

23, 24

Dynamic Characteristics

Input voltage for IMA > 60 dB

180

230

mVrms SC1 = 6 MHz;

SC2 = 6.5 MHz;
SC3 = 7 MHz;

SC1

SC2

SC3

Input-frequency band

I24

MHz

Input-resistance

23/24

Output-frequency band

O21/22

MHz

Frequency band of VCO

MHz

Mixer gain

� 8

� 4

� 2

= 470

Output-voltage range
on mixer

� 0.4

max

IMA > 55 dB;

23/24

< 180 mVrms

TDA 6160-2X

Semiconductor Group

155

TDA 6160-2X

Characteristics (cont'd)

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

Sound IF (for all three amplifiers)

Static and Dynamic Characteristics

Input-frequency band

15, 17, 19

MHz

Input voltage to
activate limiting
(

qAF

� 3 dB)

15, 17, 19

250

�

I15, 17, 19

= 10.7 MHz;

= 30 kHz;

mod

= 1 kHz

AF-output voltage

8, 11, 14

150

220

300

I15, 17, 19

= 10.7 MHz;

= 30 kHz;

I15, 17, 19

= 10 mV,

mod

= 1 kHz

Distortion factor

THD

8, 11, 14

0.2

I15, 17, 19

= 10.7 MHz;

= 30 kHz;

I15, 17, 19

= 10 mV,

mod

= 1 kHz

AM-rejection

I15, 17, 19

= 20 to

100 mV;

= 30%

AM-rejection

I15

= 2 mV;

= 30%

AF-output DC-voltage

2.2

Design Notes

Sound IF-input resistance

15/20

17/20

19/20

800

Demodulator input resistance

6/7

9/10

12/13

AF-output resistance

8, 11, 14

100

Residual IF-voltage

IF8, 11, 14

Hum suppression
(without deemphasis)

= 5 V;

= 250 mVpp;

= 50 Hz

Semiconductor Group

156

Characteristics (cont'd)

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

C Bus (SCL, SDA)

Edges SCL, SDA
Rise time
Fall time

1
300

�

Shift clock SCL
Frequency
H-pulse width
L-pulse width

SCL

0
4
4

100

kHz

�

Start
Setup time
Hold time

SUSTA

HDSTA

4
4

�

Stop
Setup time
Bus free

SUSTO

BUF

4
4

�

Data change
Setup time
Hold time

SUDAT

HDDAT

1
1

�

Inputs SCL, SDA
Input voltage

Input current

2.4

5.5
1

10
10

V
V

�

Output SDA (open collector)
Output voltage

4.5

5.5
0.4

V
V

= 2.5 k

= 3 mA

Address byte 1 = L

Address byte 2 = H or open

2.4

5.5

TDA 6160-2X

Электронный компонент: TDA6160-2X