Document Outline
- S-24C04BPHAL
- Cover
- Features
- Package
- Pin Assignment
- Block Diagram
- Absolute Maximum Ratings
- Recommended Operating Conditions
- Pin Capacitance
- Endurance
- DC Electrical Characteristics
- AC Electrical Characteristics
- Pin Functions
- Operation
- Using S-24C04BPHAL
- Precautions
- I2C Bus License
- Characteristics
- Product Code Structure
- Package drawing
Rev.1.0
_00
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Seiko Instruments Inc.
1
The S-24C04BPHAL is a 2-wire, low-power, wide-
range-operation 4k bit serial E
2
PROM organized as
512 words
8 bits. Page write and sequential read
are possible.
Features
Low power consumption
Standby:
1.0
A max. (V
CC
= 5.5 V)
Operating:
0.8 mA max. (V
CC
= 5.5 V)
0.3 mA max. (V
CC
= 3.3 V)
Wide operating voltage range:
Reading:
1.6 to 5.5 V
Writing:
1.7 to 5.5 V
Page write:
16 bytes/page
Sequential read
Operating frequency:
400 kHz (V
CC
= 5 V 10%)
Endurance:
10
6
cycles/word
Data retention:
10 years
Write protection
100%
Package
Drawing Code
Package Name
Package Tape Reel
WLP-5A HA005-A
HA005-A
HA005-A
Caution This product is intended for use in general electronic devices such as consumer
electronics, office equipment, and communications devices. Before using the product in
medical equipment or automobile equipment including car audio, keyless entry, and
engine control units, be sure to contact SII.
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
2
Seiko instruments inc.
Pin Assignment
WLP-5A
Bottom view
Table 1
Pin
Number
Pin
Name
Function
1
VCC Power
supply
2
SDA
Serial data I/O
3
WP
Write Protection pin
Connected to Vcc: Protection valid
Connected to GND: Protection invalid
4
SCL
Serial clock input
5
GND Ground
Remark See Dimensions for details of the package drawings.
Figure 1
S-24C04BPHAL
VCC
WP
SCL
SDA
GND
1
5
2
3
4
2-WIRE CMOS SERIAL E
2
PROM
Rev.1.0
_00
S-24C04BPHAL
Seiko Instruments Inc.
3
Block Diagram
VCC
GND
Serial clock
controller
Device address
comparator
Address
counter
Y decoder
Data output
ACK output
controller
Start/stop
detector
Data Register
E
2
PROM
X decoder
Selector
High-voltage generator
SCL
SDA
D
IN
D
OUT
R/W
LOAD INC
COMP
LOAD
WP
Figure 2
Absolute Maximum Ratings
Table 2
Parameter Symbol
Ratings
Unit
Power supply voltage
V
CC
-0.3 to +7.0
Input voltage
V
IN
-0.3 to V
CC
+ 0.3
Output voltage
V
OUT
-0.3 to V
CC
V
Storage temperature
T
stg
-65 to +150
C
Caution The absolute maximum ratings are rated values exceeding which the
product could suffer physical damage. These values must therefore
not be exceeded under any condition.
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
4
Seiko instruments inc.
Recommended Operating Conditions
Table 3
Parameter Symbol
Conditions
Min.
Typ.
Max.
Unit
Reading 1.6
-
5.5
Power supply voltage
V
CC
Writing 1.7
-
5.5
V
CC
= 2.5 to 5.5 V
0.7
V
CC
-
V
CC
High-level input voltage
V
IH
V
CC
= 1.6 to 2.5 V
0.8
V
CC
-
V
CC
V
CC
= 2.5 to 5.5 V
0.0
- 0.3
V
CC
Low-level input voltage
V
IL
V
CC
= 1.6 to 2.5 V
0.0
- 0.2
V
CC
V
Operating temperature
T
opr
-
-40
-
+85
C
Pin Capacitance
Table 4
(Ta
= 25C, f = 1.0 MHz, Vcc = 5 V)
Parameter Symbol
Conditions
Min.
Typ.
Max.
Unit
Input capacitance
C
IN
V
IN
= 0 V (SCL, WP)
-
-
10
Input/output capacitance
C
I/O
V
I/O
= 0 V (SDA)
-
-
10
pF
Endurance
Table 5
Parameter Symbol
Operating Temperature
Min. Typ. Max. Unit
Endurance
N
W
-40 to +85C 10
6
-
- Cycles/word
2-WIRE CMOS SERIAL E
2
PROM
Rev.1.0
_00
S-24C04BPHAL
Seiko Instruments Inc.
5
DC Electrical Characteristics
Table 6
V
CC
= 4.5 to 5.5 V V
CC
= 2.5 to 4.5 V V
CC
= 1.6 to 2.5 V
Parameter Symbol
Conditions
Min. Typ. Max. Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Current consumption
(READ)
I
CC1
f
= 100 kHz
-
-
0.8
*1
-
-
0.3
-
-
0.2
Current consumption
(PROGRAM)
I
CC2
f
= 100 kHz
-
-
4.0
-
-
1.5
-
-
1.5
*2
mA
*1. f
= 400 kHz
*2. V
CC
= 1.7 to 2.5 V
Table 7
V
CC
= 4.5 V to 5.5 V V
CC
= 2.5 to 4.5 V V
CC
= 1.6 to 2.5 V
Parameter Symbol Conditions
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Unit
Standby current
consumption
I
SB
V
IN
= V
CC
or GND
-
-
1.0
-
-
0.6
-
-
0.4
Input current
leakage
I
LI
V
IN
= GND to V
CC
-
0.1 1.0 -
0.1 1.0 -
0.1 1.0
Output current
leakage
I
LO
V
OUT
= GND to V
CC
-
0.1 1.0 -
0.1 1.0 -
0.1 1.0
A
I
OL
= 3.2 mA
-
-
0.4
-
-
0.4
-
-
-
Low-level
output voltage
V
OL
I
OL
= 1.5 mA
-
-
0.3
-
-
0.3
-
-
0.5
Current address
hold voltage
V
AH
-
1.5
-
5.5 1.5 -
4.5 1.5 -
2.5
V
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
6
Seiko instruments inc.
AC Electrical Characteristics
Table 8 Measurement Conditions
Input pulse voltage
0.1
V
CC
to 0.9
V
CC
Input pulse rise/fall time
20 ns
Output judgment voltage 0.5 V
CC
Output load
100 pF
+ pull-up resistance 1.0 k
SDA
C
= 100 pF
V
CC
R
= 1.0 k
Figure 3 Output Load Circuit
Table 9
V
CC
= 4.5 V to 5.5 V
V
CC
= 1.6 V to 4.5 V
Parameter Symbol
Min. Typ. Max. Min. Typ. Max.
Unit
SCL clock frequency
f
SCL
0
- 400 0 -
100 kHz
SCL clock time "L"
t
LOW
1.0
-
-
4.7
-
-
SCL clock time "H"
t
HIGH
0.9
-
-
4.0
-
-
SDA output delay time
t
AA
0.1
-
0.9 0.1
-
3.5
s
SDA output hold time
t
DH
50
-
-
100
-
-
ns
Start condition setup time
t
SU, STA
0.6
-
-
4.7
-
-
Start condition hold time
t
HD, STA
0.6
-
-
4.0
-
-
s
Data input setup time
t
SU, DAT
100
-
-
200
-
-
Data input hold time
t
HD, DAT
0
-
-
0
-
-
ns
Stop condition setup time
t
SU, STO
0.6
-
-
4.7
-
-
SCL
SDA rise time
t
R
-
-
0.3
-
-
1.0
SCL
SDA fall time
t
F
-
-
0.3
-
-
0.3
Bus release time
t
BUF
1.3
-
- 4.7 -
-
s
Noise suppression time
t
I
-
-
50
-
-
100 ns
SCL
SDA IN
SDA OUT
t
BUF
t
R
t
SU, STO
t
SU, DAT
t
HD, DAT
t
DH
t
AA
t
HIGH
t
LOW
t
HD, STA
t
SU, STA
t
F
Figure 4 Bus Timing
2-WIRE CMOS SERIAL E
2
PROM
Rev.1.0
_00
S-24C04BPHAL
Seiko Instruments Inc.
7
Table 10
Item Symbol
Min. Typ. Max.
Unit
Write time
t
WR
4.0 10.0
ms
SCL
SDA
D0
Write data
Acknowledge
Stop condition
Start condition
t
WR
Figure 5 Write Cycle Timing
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
8
Seiko instruments inc.
Pin Functions
1. SDA (serial data input/output) pin
The SDA pin is used for bidirectional transfer of serial data. It consists of a signal input pin and an Nch
open-drain transistor output pin. Usually pull up the SDA line to V
CC
via a resistor, and use it with other
open-drain or open-collector output devices connected in a wired-OR configuration.
2. SCL (serial clock input) pin
The SCL pin is used for serial clock input. It is capable of processing signals at the rising and falling
edges of the SCL clock input signal. Make sure the rise time and fall time conform to the specifications.
3. WP pin
The WP pin is used for write protection. When there is no need for write protection, connect the pin to
GND; when there is a need for write protection, connect the pin to V
CC
.
2-WIRE CMOS SERIAL E
2
PROM
Rev.1.0
_00
S-24C04BPHAL
Seiko Instruments Inc.
9
Operation
1. Start condition
When the SDA line changes from "H" to "L" with the SCL line at "H", the device is in the start condition.
All operations begin from the start condition.
2. Stop condition
When the SDA line changes from "L" to "H" with the SCL line at "H", the device is in the stop condition.
When the device receives the stop condition signal during a read sequence, the read operation is
interrupted, and the device enters standby mode.
When the device receives the stop condition signal during a write sequence, the retrieval of write data is
halted, and rewriting the E
2
PROM starts.
t
SU, STA
t
HD, STA
t
SU, STO
Start condition
Stop condition
SCL
SDA
Figure 6 Start/Stop Condition
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
10
Seiko instruments inc.
3. Data transfer
Changing the SDA line while the SCL line is "L" allows the data to be transferred.
A start or stop condition is recognized when the SDA line changes while the SCL line is "H".
t
SU, DAT
t
HD, DAT
SCL
SDA
Figure 7 Data Transfer Timing
4. Acknowledgment
8 bits of data are transferred in succession. The device on the system bus that receives the data changes
the SDA line to "L" during the 9th clock cycle and outputs the acknowledge signal to inform that it has
received the data.
The device does not output the acknowledge signal while the E
2
PROM is being rewritten.
1
8
9
Acknowledge
output
t
AA
t
DH
Start condition
SCL
(E
2
PROM input)
SDA
(Master output)
SDA
(E
2
PROM output)
Figure 8 Acknowledge Output Timing
2-WIRE CMOS SERIAL E
2
PROM
Rev.1.0
_00
S-24C04BPHAL
Seiko Instruments Inc.
11
5. Device addressing
To perform data communications, the master device mounted on the system outputs the start condition signal
to the slave device. Next, the master device outputs a 7-bit device address and a 1-bit read/write instruction
code onto the SDA bus.
The higher 4 bits of the device address are called the "Device Code", and are fixed to "1010". The following 2
bits are "don't care" bits.
When the comparison results match, the slave device outputs the acknowledge signal during the 9th clock
cycle.
Page
address
1
0
1
0
X
X
P0
R / W
Device code
S-24C04BPHAL
MSB
LSB
Don't
care
Remark X: Don't care
Figure 9 Device Address
In the S-24C04BPHAL, the 7th bit is a page address bit.
Accordingly, when P0
= 0, the first half of the memory area (2 Kb: addresses 000h to 0FFh) is selected; when
P0
= 1, the second half of the memory area (2 Kb; addresses 100h to 1FFh) are selected.
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
12
Seiko instruments inc.
6. Write operation
6.1 Byte write
When
the
E
2
PROM receives a 7-bit device address and the 1-bit read/write instruction code "0", following
the start condition signal, it outputs the acknowledge signal.
Next, when the E
2
PROM receives an 8-bit word address, it outputs the acknowledge signal.
After the E
2
PROM receives 8-bit write data and outputs the acknowledge signal, it receives the stop
condition signal. Next, rewriting the specified memory address of the E
2
PROM starts.
While the E
2
PROM is being rewritten, all operations are prohibited and the acknowledge signal is not
output.
X X P0
S
T
A
R
T
1
0 1 0
W
R
I
T
E
DEVICE
ADDRESS
R
/
W
M
S
B
SDA line
ADR INC
(ADDRESS INCREMENT)
A
C
K
L
S
B
0
WORD ADDRESS
S
T
O
P
DATA
W7 W6 W5 W4 W3 W2 W1 W0
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
A
C
K
Figure 10 Byte Write
2-WIRE CMOS SERIAL E
2
PROM
Rev.1.0
_00
S-24C04BPHAL
Seiko Instruments Inc.
13
6.2 Page write
Up to 16 bytes per page can be written in the S-24C04BPHAL.
Basic data transfer procedures are the same as those in "Byte write". The S-24C04BPHAL performs page
write by successively receiving 8-bit write data sized pages.
When the E
2
PROM receives a 7-bit device address and the 1-bit read/write instruction code "0" following
the start condition signal, it outputs the acknowledge signal. When the E
2
PROM receives an 8-bit word
address, it outputs the acknowledge signal. After the E
2
PROM receives 8-bit write data and outputs the
acknowledge signal, it receives 8-bit write data corresponding to the next word address, and outputs the
acknowledge signal. The E
2
PROM repeats reception of 8-bit write data and output of the acknowledge
signal in succession and can receive write data corresponding to the maximum page size. When the stop
condition signal is received, E
2
PROM corresponding to the size of the page on which write data starting
from the specified memory address is received starts to be rewritten.
S
T
A
R
T
1
0 1 0
W
R
I
T
E
S
T
O
P
DEVICE
ADDRESS
WORD ADDRESS (n)
R
/
W
M
S
B
SDA
line
X X P0
A
C
K
L
S
B
A
C
K
A
C
K
0
D7 D6 D5 D4 D3 D2 D1 D0
D7
D0
D7
D0
A
C
K
ADR INC
ADR INC
A
C
K
DATA (n) DATA
(n + 1)
DATA (n + x)
W7 W6 W5 W4 W3 W2 W1 W0
ADR INC
Figure 11 Page Write
The lower 4 bits of the word address are automatically incremented each time when the E
2
PROM receives
8-bit write data. Even when the write data exceeds 16 bytes, the higher 4 bits of the word address and
page address P0 remain unchanged, and the lower 4 bits are rolled over and overwritten
.
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
14
Seiko instruments inc.
6.3 Acknowledgment polling
Acknowledgment polling is used to ascertain when rewriting the E
2
PROM is finished. After the E
2
PROM
receives the stop condition signal and once rewriting starts, all operations are prohibited and the E
2
PROM
cannot respond to the signals transmitted by the master device. Accordingly, the master device transmits
the start condition signal, the device address, and read/write instruction code to the E
2
PROM (namely, the
slave device) to detect the response of the slave device. This allows users to know that rewriting the
E
2
PROM is finished. That is, if the slave device does not output the acknowledge signal, the E
2
PROM is
being rewritten; when the slave device outputs the acknowledge signal, rewriting has been completed. It is
recommended to use a read instruction of "1" for the read/write instruction code transmitted by the master
device.
6.4 Write protection
The S-24C04BPHAL is provided with a write protection function. When the WP pin is connected to V
CC
,
writing to any memory area is prohibited. When the WP pin is connected to GND, write protection is
disabled, and writing in all memory areas is possible. When the write protection function is not used,
always connect the WP pin to GND. Write protection is valid within the operating supply voltage range.
2-WIRE CMOS SERIAL E
2
PROM
Rev.1.0
_00
S-24C04BPHAL
Seiko Instruments Inc.
15
7. Read
7.1 Current address read
The E
2
PROM holds the last accessed memory address during both writing and reading. The memory
address is retained as long as the power voltage is the retention voltage V
AH
or more. Accordingly, when
the master device recognizes the position of the address pointer inside the E
2
PROM, data can be read from
the memory address of the current address pointer without specifying a word address. This is called
"Current Address Read".
"Current Address Read" is explained for when the address counter inside the E
2
PROM is address "n".
When the E
2
PROM receives a 7-bit device address and the 1-bit read/write instruction code "1", following
the start condition signal, it outputs the acknowledge signal.
Next, 8-bit data at address "n" is output from the E
2
PROM, in synchronization with the SCL clock.
The address counter is incremented to address n
+ 1 at the falling edge of the SCL clock at which the 8th
bit of data is output.
The master device does not output the acknowledge signal and transmits the stop
condition signal to finish reading.
S
T
A
R
T
1 0 1 0
R
E
A
D
S
T
O
P
DEVICE
ADDRESS
R
/
W
M
S
B
SDA line
ADR INC
X X P0
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
L
S
B
1
DATA
No ACK from
master device
Figure 12 Current Address Read
For recognition of the address pointer inside the E
2
PROM, take into consideration the following:
The memory address counter inside the E
2
PROM is automatically incremented for every falling edge of the
SCL clock at which the 8th bit of data is output during reading. During writing, the higher bits of the memory
address (higher 4 bits of the word address) are left unchanged and are not incremented at any falling of the
SCL clock when the 8th bit of the write data is received.
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
16
Seiko instruments inc.
7.2 Random read
Random read is a mode used when data is read from arbitrary memory addresses.
To load a memory address into the address counter inside the E
2
PROM, first perform a dummy write
following the procedure below.
When the E
2
PROM receives a 7-bit device address and the 1-bit read/write instruction code "0" following the
start condition signal, it outputs the acknowledge signal.
Next, the E
2
PROM receives an 8-bit word address and outputs the acknowledge signal. The memory
address has now been loaded into the address counter of the E
2
PROM.
Following this, the E
2
PROM receives the write data during byte or page writing. However, data reception is
not performed during dummy write.
The memory address is loaded into the memory address counter inside the E
2
PROM during dummy write.
After that, the master device can read the data starting from the arbitrary memory address by transmitting a
new start condition signal and performing the same operation as that in the "Current Address Read".
That is, when the E
2
PROM receives a 7-bit device address and the 1-bit read/write instruction code "1"
following the start condition signal, it outputs the acknowledge signal.
Next, 8-bit data is output from the E
2
PROM in synchronization with the SCL clock. The master device does
not output an acknowledge
signal and transmits the stop condition signal instead. Reading is then complete.
SDA
line
S
T
A
R
T
1 0 1 0
W
R
I
T
E
DEVICE
ADDRESS
WORD ADDRESS (n)
R
/
W
M
S
B
X X P0
A
C
K
L
S
B
W7
W6
W5
W4
W3
W2
W1
W0
A
C
K
0
DUMMY WRITE
S
T
O
P
S
T
A
R
T
1 0 1 0
R
E
A
D
DEVICE
ADDRESS
R
/
W
M
S
B
X X P0
A
C
K
L
S
B
1
No ACK from
master device
ADR INC
DATA
D7 D6 D5 D4 D3 D2 D1 D0
Figure 13 Random Read
2-WIRE CMOS SERIAL E
2
PROM
Rev.1.0
_00
S-24C04BPHAL
Seiko Instruments Inc.
17
7.3 Sequential read
When the E
2
PROM receives a 7-bit device address and the 1-bit read/write instruction code "1" in both
current and random read operations following the start condition signal, it outputs the acknowledge signal.
When 8-bit data is output from the E
2
PROM, in synchronization with the SCL clock, the memory address
counter inside the E
2
PROM is automatically incremented at the falling edge of the SCL clock at which the
8th data is output.
When the master device transmits the acknowledge signal, the next memory address data is output.
When the master device transmits the acknowledge signal, the memory address counter inside the
E
2
PROM is incremented and data can be read in succession. This is called "Sequential Read".
When the master device does not output an acknowledge signal and transmits the stop condition signal, the
read operation is finished.
Data can be read in the "Sequential Read" mode in succession. When the memory address counter reaches
the last word address, it rolls over to the first memory address.
R
E
A
D
S
T
O
P
DEVICE
ADDRESS
R
/
W
ADR INC
A
C
K
A
C
K
A
C
K
1
ADR INC
A
C
K
ADR INC
SDA
line
DATA (n)
D7
D0
D7
D0
D7
D0
D7
D0
DATA (n +1 )
DATA (n + 2)
DATA (n + x)
No ACK from
master device
ADR INC
Figure 14 Sequential Read
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
18
Seiko instruments inc.
8. Address increment timing
The address increment timing is as follows. During a read operation, the memory address counter is
automatically incremented at the falling edge of the SCL clock (where the 8th bit of read data is output).
During a write operation, the memory address counter is also automatically incremented at the falling edge of
the SCL clock when the 8th bit of write data is fetched.
SCL
SDA
R / W
= 1
Address increment
8 9 1
8 9
D7 output
D0 output
ACK output
Figure 15 Address Increment Timing in Read Operation
SCL
SDA R
/
W
= 0
8 9 1
8 9
D7 input
D0 input
ACK output
ACK output
Address increment
Figure 16 Address Increment Timing in Write Operation
2-WIRE CMOS SERIAL E
2
PROM
Rev.1.0
_00
S-24C04BPHAL
Seiko Instruments Inc.
19
Using S-24C04BPHAL
1. Adding a pull-up resistor to SDA I/O pin and SCL input pin
Add a 1 k
to 5 k pull-up resistor to the SCL input pin
*1
and the SDA I/O pin in order to enable the
functions of the I
2
C Bus protocol. Normal communication cannot be provided without a pull-up resistor.
*1. When the SCL input pin of the E
2
PROM is connected to a tri-state output pin of the microprocessor,
connect the same pull-up resistor to prevent a high impedance status from being input to the SCL input
pin.
This protects the E
2
PROM from malfunction due to an undefined output (high impedance) from the tri-
state pin when the microprocessor is reset when the voltage drops.
2. Slave address
The S-24C04BPHAL does not have slave address pins (A0, A1, A2). Therefore two or more of this IC cannot
be used on the same bus.
However, slave addresses can be used without changing the communication software because they are
arbitrary addresses in communication with the master device.
1
0
1
0
x
x
P0
R/W
Don't care
SDA line
MSB
LSB
ACK
Figure 17
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
20
Seiko instruments inc.
3. I/O pin equivalent circuit
The I/O pins of this IC do not include pull-up and pull-down resistors. The SDA pin is an open-drain output.
The following shows the equivalent circuits.
SCL
Figure 18 SCL Pin
WP
Figure 19 WP Pin
SDA
Figure 20 SDA Pin
2-WIRE CMOS SERIAL E
2
PROM
Rev.1.0
_00
S-24C04BPHAL
Seiko Instruments Inc.
21
4. Maximum effectiveness of write protection
The following conditions must be satisfied to prevent erroneous writing at power-on due to write protection.
<1> Set the WP pin to high level at a time other than when the write instruction is being executed, including
during power-on or off.
<2> Adjust the phase after power-on.
Pulling up the WP pin to V
CC
to always enable the WP pin at the absolute maximum rated voltage or lower
prohibits writing all the time regardless of the conditions of the VCC, SDA, and SCL pins.
5. Matching phases while E
2
PROM is accessed
The S-24C04BPHAL does not have a pin for resetting (the internal circuit), therefore, the E
2
PROM cannot
be forcibly reset externally. If a communication interruption occurs in the E
2
PROM, it must be reset by
software.
For example, even if a reset signal is input to the microprocessor, the internal circuit of the E
2
PROM is not
reset as long as the stop condition is not input to the E
2
PROM. In other words, the E
2
PROM retains the
same status and cannot shift to the next operation. This symptom applies to the case when only the
microprocessor is reset when the power supply voltage drops. With this status, if the power supply voltage
is restored, reset the E
2
PROM (after matching the phase with the microprocessor) and input an instruction.
The following shows this reset method.
[How to reset E
2
PROM]
The E
2
PROM can be reset by the start and stop instructions. When the E
2
PROM is reading data "0" or
is outputting the acknowledge signal, 0 is output to the SDA line. In this status, the microprocessor
cannot output an instruction to the SDA line. In this case, terminate the acknowledge output operation
or read operation, and then input a start instruction. Figure 21 shows this procedure.
First, input the condition. Then transmit 9 clocks (dummy clocks) of SCL. During this time, the
microprocessor sets the SDA line to high level. By this operation, the E
2
PROM interrupts the
acknowledge output operation or data output, so input the start condition
*1
. When a start condition is
input, the E
2
PROM is reset. To make doubly sure, input the stop condition to the E
2
PROM. Normal
operation is then possible.
1
2
8
9
SCL
SDA
Start
condition
Stop
condition
Start
condition
Dummy clock
Figure 21 Resetting E
2
PROM
*1. After 9 clocks (dummy clocks), if the SCL clock continues to be output without a start condition
being input, a write operation may be started upon receipt of a stop condition. To prevent this, input
a start condition after 9 clocks (dummy clocks).
Remark It is recommended to perform the above reset using dummy clocks when the system is
initialized after the power supply voltage has been raised.
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
22
Seiko instruments inc.
6. Acknowledge check
The I
2
C Bus protocol includes an acknowledge check function as a handshake function to prevent a
communication error. This function allows detection of a communication failure during data communication
between the microprocessor and E
2
PROM. This function is effective to prevent malfunction, so it is
recommended to perform an acknowledge check on the microprocessor side.
7. Built-in power-on-clear circuit
E
2
PROMs have a built-in power-on-clear circuit that initializes the E
2
PROM. Unsuccessful initialization may
cause a malfunction. For the power-on-clear circuit to operate normally, the following conditions must be
satisfied for raising the power supply voltage.
7.1 Raising power supply voltage
Raise the power supply voltage, starting at 0.2 V maximum, so that the voltage reaches the power supply
voltage to be used within the time defined by t
RISE
as shown in Figure 22.
For example, when the power supply voltage to be used is 5.0 V, t
RISE
is 200 ms as shown in Figure 23.
The power supply voltage must be raised within 200 ms.
0.2 V
V
INIT
(Max.)
t
INIT
*2
(Max.)
t
RISE
(Max.)
Power supply voltage (V
CC
)
0 V
*1
*1. 0 V means there is no difference in potential between the V
CC
pin and the
GND pin of the E
2
PROM.
*2. t
INIT
is the time required to initialize the E
2
PROM. No instructions are
accepted during this time.
Figure 22 Raising Power Supply Voltage
2-WIRE CMOS SERIAL E
2
PROM
Rev.1.0
_00
S-24C04BPHAL
Seiko Instruments Inc.
23
Rise time (t
RISE
) Max.
[ms]
Power supply voltage
(V
CC
)
[V]
50
5.0
4.0
3.0
2.0
100 150 200
For example:
If your E
2
PROM supply voltage = 5.0 V, raise the power supply
voltage to 5.0 V within 200 ms.
Figure 23 Raising Time of Power Supply Voltage
When initialization is successfully completed via the power-on-clear circuit, the E
2
PROM enters the standby
status.
If the power-on-clear circuit does not operate, the following are the possible causes.
(1) Because the E
2
PROM has not been initialized, an instruction formerly input is valid or an instruction
may be inappropriately recognized. In this case, writing may be performed.
(2) The voltage may have dropped due to power off while the E
2
PROM is being accessed. Even if the
microprocessor is reset due to the low power voltage, the E
2
PROM may malfunction unless the power-
on-clear operation conditions of E
2
PROM are satisfied. For the power-on-clear operation conditions of
E
2
PROM, refer to 7.1 Raising power supply voltage.
If the power-on-clear circuit does not operate, match the phase (reset) so that the internal E
2
PROM circuit is
normally reset. The statuses of the E
2
PROM immediately after the power-on-clear circuit operates and
when phase is matched (reset) are the same.
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
24
Seiko instruments inc.
7.2 Wait for the initialization sequence to end
The E
2
PROM executes initialization during the time that the supply voltage is increasing to its normal value.
All instructions must wait until after initialization. The relationship between the initialization time (t
INIT
) and
rise time (t
RISE
) is shown in Figure 24.
Rise time (t
RISE
)
[s]
E
2
PROM initialization
time (t
INIT
) Max.
[s]
100 m
10 m
1.0 m
100
10
1.0
1.0
10 100
1.0 m 10 m 100 m
Figure 24 Initialization Time of E
2
PROM
2-WIRE CMOS SERIAL E
2
PROM
Rev.1.0
_00
S-24C04BPHAL
Seiko Instruments Inc.
25
8. Data hold time (t
HD, DAT
=
=
=
= 0 ns)
If SCL and SDA of the E
2
PROM are changed at the same time, it is necessary to prevent the start/stop
condition from being mistakenly recognized due to the effect of noise. If a start/stop condition is mistakenly
recognized during communication, the E
2
PROM enters the standby status.
It is recommended that SDA is delayed from the falling edge of SCL by 0.3
s maximum in the S-
24C04BPHAL. This is to prevent time lag caused by the load of the bus line from generating the stop (or
start) condition.
SCL
SDA
t
HD, DAT
= 0.3
s Max.
Figure 25 E
2
PROM Data Hold Time
9. SDA pin and SCL pin noise elimination time
The S-24C04BPHAL includes a built-in low-pass filter to eliminate noise at the SDA and SCL pins. This
means that if the power supply voltage is 5.0 V (at room temperature), noise with a pulse width of 150 ns or
less can be eliminated.
The guaranteed performance is t
I
= 100 ns. For details, refer to Table 9.
Noise elimination time (t
I
) Max.
[ns]
Power supply
voltage (V
CC
)
[V]
5.5
5.0
4.5
4.0
100
150 200
Figure 26 Noise Elimination Time for SDA and SCL Pins
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
26
Seiko instruments inc.
10. Trap: E
2
PROM operation in case that the stop condition is received during write operation before
receiving the defined data value (less than 8-bit) to SCL pin
When the E
2
PROM receives the stop condition signal compulsorily, during receiving 1 byte of write data,
"write" operation is aborted.
When the E
2
PROM receives the stop condition signal after receiving 1 byte or more of data for "page write",
8-bit of data received normally before receiving the stop condition signal can be written.
11. Trap: E
2
PROM operation and write data in case that write data is input more than defined page size at
"page write"
When write data is input more than defined page size at page write operation, for example, S-24C04BPHAL
(which can be executed 16-byte page write) is received data more than 17 byte, 8-bit data of the 17th byte
is over written to the first byte in the same page. Data over the capacity of page address cannot be written.
12. Trap: Severe environments
Absolute maximum ratings: Do not operate these ICs in excess of the absolute max ratings, as listed on the
data sheet. Exceeding the supply voltage rating can cause latch-up.
Operations with moisture on the E
2
PROM pins may occur malfunction by short-circuit between pins.
Especially, in occasions like picking the E
2
PROM up from low temperature tank during the evaluation. Be
sure that not remain frost on E
2
PROM pin to prevent malfunction by short-circuit.
Also attention should be paid in using on environment, which is easy to dew for the same reason.
2-WIRE CMOS SERIAL E
2
PROM
Rev.1.0
_00
S-24C04BPHAL
Seiko Instruments Inc.
27
Precautions
The side of device silicon substrate is exposed to the marking side of device package. Since this portion
has lower strength against the mechanical stress than the standard plastic package, chip, crack, etc
should be careful of the handing of a package enough. Moreover, the exposed side of silicon has
electrical potential of device substrate, and needs to be kept out of contact with the external potential.
In this package, the overcoat of the resin of translucence is carried out on the side of transistor area.
Keep it mind that it may affect the characteristic of a package when exposed a device in the bottom of a
high light source.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
SII claims no responsibility for any and all disputes arising out of or in connection with any infringement
by the products including this IC of patents owned by a third party.
I
2
C Bus License
Purchase of the I
2
C components of Seiko Instruments Inc., conveys a license under the Philips I
2
C Patent.
The rights to use these components in an I
2
C system is granted provided that the system conforms to the
I
2
C Standard Specification as defined by Philips.
Please note that a product or a system incorporating this IC may infringe the Philips I
2
C Patent Rights
depending upon its configuration.
In the event of such infringement, Seiko Instruments Inc. shall not bear any responsibility for any matters
with regard to and arising from such patent infringement.
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
28
Seiko instruments inc.
Characteristics
1. DC Characteristics
1.1 Current consumption (READ) I
CC1
-
Ambient temperature Ta
1.2 Current consumption (READ) I
CC1
-
Ambient temperature Ta
I
CC1
(
A)
-40 0
85
200
100
V
CC
= 5.5 V
f
SCL
= 100 kHz
DATA
= 0101
0
I
CC1
(
A)
200
100
V
CC
= 3.3 V
f
SCL
= 100 kHz
DATA
= 0101
0
-40
0 85
Ta
(
C)
Ta
(
C)
1.3 Current consumption (READ) I
CC1
-
Ambient temperature Ta
1.4 Current consumption (READ) I
CC1
-
Power supply voltage V
CC
I
CC1
(
A)
40
20
V
CC
= 1.8 V
f
SCL
= 100 kHz
DATA
= 0101
0
-40
0 85
I
CC1
(
A)
100
50
0
2 3 4 5 6 7
Ta
= 25C
f
SCL
= 100 kHz
DATA
= 0101
Ta (
C)
V
CC
(V)
1.5 Current consumption (READ) I
CC1
-
Power supply voltage V
CC
1.6 Current consumption (READ) I
CC1
-
Clock frequency f
SCL
I
CC1
(
A)
200
100
0
2 3 4 5 6 7
Ta
= 25C
f
SCL
= 400 kHz
DATA
= 0101
I
CC1
(
A)
V
CC
(V)
f
SCL
(Hz)
200
100
0
V
CC
= 5.0 V
Ta
= 25C
100 k 200 k 300 k 400 k
2-WIRE CMOS SERIAL E
2
PROM
Rev.1.0
_00
S-24C04BPHAL
Seiko Instruments Inc.
29
1.7 Current consumption (PROGRAM) I
CC2
-
Ambient temperature Ta
1.8 Current consumption (PROGRAM) I
CC2
-
Ambient temperature Ta
I
CC2
(m
A
)
1.0
0.5
V
CC
= 5.5 V
0
-40
0 85
I
CC2
(m
A
)
1.0
0.5
V
CC
= 3.3 V
0
-40 0
85
Ta
(
C)
Ta
(
C)
1.9 Current consumption (PROGRAM) I
CC2
-
Ambient temperature Ta
1.10 Current consumption (PROGRAM) I
CC2
-
Power supply voltage V
CC
I
CC2
(m
A
)
1.0
0.5
V
CC
= 2.5 V
0
-40
0 85
I
CC2
(m
A
)
2 3
6 7
1.0
0.5
0
4
5
Ta
= 25C
Ta (
C)
V
CC
(V)
1.11 Standby current consumption I
SB
-
Ambient temperature Ta
1.12 Input current leakage I
LI
-
Ambient temperature Ta
I
SB
(A
)
10
-7
10
-8
10
-9
10
-10
V
CC
= 5.5 V
10
-11
-40
0 85
I
LI
(
A)
1.0
0.5
V
CC
= 5.5 V
SDA, SCL, WP
= 0 V
0
-40
0 85
Ta (
C)
Ta (
C)
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
30
Seiko instruments inc.
1.13 Input current leakage I
LI
-
Ambient temperature Ta
1.14 Output current leakage I
LO
-
Ambient temperature Ta
I
LI
(
A)
1.0
0.5
0
-40
0 85
V
CC
= 5.5 V
SDA, SCL, WP
= 5.5 V
I
LO
(
A)
1.0
0.5
V
CC
= 5.5 V
SDA
= 0 V
0
-40
0
85
Ta (
C)
Ta (
C)
1.15 Output current leakage I
LO
-
Ambient temperature Ta
1.16 Low-level output voltage V
OL
-
Low-level output current I
OL
I
LO
(
A)
1.0
0.5
V
CC
= 5.5 V
SDA
= 5.5 V
0
-40
0 85
V
OL
(V
)
0.2
0.1
0
1
2 3 4 5 6
V
CC
= 3.3 V
V
CC
= 5 V
Ta
= 25C
Ta
(
C)
I
OL
(mA)
1.17 Low-level output voltage V
OL
-
Ambient temperature Ta
1.18 Low-level output voltage V
OL
-
Ambient temperature Ta
V
OL
(V
)
0.3
0.2
V
CC
= 4.5 V
I
OL
= 3.2 mA
-40 0
85
0.1
V
OL
(V
)
0.3
0.2
V
CC
= 1.8 V
I
OL
= 100 A
-40
0 85
0.1
Ta (
C)
Ta (
C)
2-WIRE CMOS SERIAL E
2
PROM
Rev.1.0
_00
S-24C04BPHAL
Seiko Instruments Inc.
31
1.19 Low-level output current I
OL
-
Ambient temperature Ta
1.20 Low-level output current I
OL
-
Ambient temperature Ta
I
OL
(m
A
)
20
10
V
CC
= 4.5 V
V
OL
= 0.45 V
0
-40
0 85
I
OL
(m
A
)
2.0
1.0
V
CC
= 1.8 V
V
OL
= 0.1 V
0
-40 0
85
Ta (
C)
Ta (
C)
1.21 High input inversion voltage V
IH
-
Power supply voltage V
CC
1.22 High input inversion voltage V
IH
-
Ambient temperature Ta
V
IH
(V
)
Ta
= 25C
SDA, SCL, WP
1.0
0
2.0
3.0
1 2 3 4 5 6 7
V
IH
(V
)
V
CC
= 5.0 V
SDA, SCL, WP
1.0
0
2.0
3.0
-40
0 85
V
CC
(V)
Ta (
C)
1.23 Low input inversion voltage V
IL
-
Power supply voltage V
CC
1.24 Low input inversion voltage V
IL
-
Ambient temperature Ta
V
IL
(V
)
Ta
= 25C
SDA, SCL, WP
1.0
0
2.0
3.0
1 2 3 4 5 6 7
V
IL
(V
)
1.0
0
2.0
3.0
-40
0 85
V
CC
= 5.0 V
SDA, SCL, WP
V
CC
(V)
Ta (
C)
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
32
Seiko instruments inc.
2. AC Characteristics
2.1
Maximum operating frequency fmax
-
Power supply voltage V
CC
2.2 Write time t
WR
-
Power supply voltage V
CC
f
ma
x
(H
Z
)
10 k
2 3 4 5
Ta
= 25C
1
100 k
1 M
t
WR
(m
s
)
4
2
2 3 4 5 6 7
Ta
= 25C
1
1
3
V
CC
(V)
V
CC
(V)
2.3 Write time t
WR
-
Ambient temperature Ta
2.4 Write time t
WR
-
Ambient temperature Ta
t
WR
(m
s
)
6
4
V
CC
= 4.5 V
-40 0
85
2
t
WR
(m
s
)
6
4
V
CC
= 2.5 V
-40
0 85
2
Ta (
C)
Ta (
C)
2.5 SDA output delay time t
AA
-
Ambient temperature Ta
2.6 SDA output delay time t
AA
-
Ambient temperature Ta
t
AA
(
s)
1.5
1.0
V
CC
= 4.5 V
-40
0
85
0.5
t
AA
(
s)
1.5
1.0
V
CC
= 2.7 V
-40
0 85
0.5
Ta (
C)
Ta (
C)
2-WIRE CMOS SERIAL E
2
PROM
Rev.1.0
_00
S-24C04BPHAL
Seiko Instruments Inc.
33
2.7 SDA output delay time t
AA
-
Ambient temperature Ta
t
AA
(
s)
3.0
2.0
V
CC
= 1.8 V
-40 0
85
1.0
Ta (
C)
2-WIRE CMOS SERIAL E
2
PROM
S-24C04BPHAL
Rev.1.0
_00
34
Seiko instruments inc.
Product Code Structure
S-24C04BP HA L - TF
IC direction in tape specification
Operating voltage range
L : Writing 1.7 to 5.5 V, reading 1.6 to 5.5 V
Package code
HA : WLP type A
Product name
S-24C04BP : 4k bit
1.660.02
A
0.06 S
S
(0.866)
5-(0.25)
0.05
M
S A B
1
3
4
0.250.02
0.150.03
5
0.6max.
2
1.210.02
0.6max.
0.5
0.40.02
0.1
No.
TITLE
SCALE
UNIT
No. HA005-A-P-SD-1.0
WLP-5A-A-PKG Dimensions
HA005-A-P-SD-1.0
Seiko Instruments Inc.
B
1
2
3
4
5
WP
VCC
SCL
SDA
GND
Pin No.
Pin name
No.
TITLE
SCALE
UNIT
mm
Seiko Instruments Inc.
No. HA005-A-C-SD-1.0
HA005-A-C-SD-1.0
WLP-5A-A-Carrier Tape
0.65
0.180.05
Feed direction
2.00.05
4.00.1
1.5
+0.1
-0
0.50.05
2.00.1
4.00.1
1.1
0.7
2.05
0.9
Count mark(R0.3,Depth 0.2)
(Every 10 pockets)
1
3
4 5
1.75
No.
TITLE
SCALE
UNIT
mm
Seiko Instruments Inc.
No. HA005-A-R-SD-1.0
HA005-A-R-SD-1.0
WLP-5A-A-Reel
QTY.
3,000
12.5max.
9.00.3
130.2
Enlarged drawing in the central part
The information described herein is subject to change without notice.
Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.
When the products described herein are regulated products subject to the Wassenaar Arrangement or other
agreements, they may not be exported without authorization from the appropriate governmental authority.
Use of the information described herein for other purposes and/or reproduction or copying without the
express permission of Seiko Instruments Inc. is strictly prohibited.
The products described herein cannot be used as part of any device or equipment affecting the human
body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus
installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc.
Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.
PDF 
ZIP