Document Outline

• TABLE OF CONTENTS
• LIST OF FIGURES AND TABLES
• 1. SYSTEM OVERVIEW
  • Table 1.1. Product Selection Guide
  • Figure 1.1. C8051F020 Block Diagram
  • Figure 1.2. C8051F021 Block Diagram
  • Figure 1.3. C8051F022 Block Diagram
  • Figure 1.4. C8051F023 Block Diagram
  • 1.1. CIP-51� Microcontroller Core
    • 1.1.1. Fully 8051 Compatible
    • 1.1.2. Improved Throughput
    • Figure 1.5. Comparison of Peak MCU Execution Speeds
    • 1.1.3. Additional Features
    • Figure 1.6. On-Board Clock and Reset
  • 1.2. On-Chip Memory
    • Figure 1.7. On-Chip Memory Map
  • 1.3. JTAG Debug and Boundary Scan
    • Figure 1.8. Development/In-System Debug Diagram
  • 1.4. Programmable Digital I/O and Crossbar
    • Figure 1.9. Digital Crossbar Diagram
  • 1.5. Programmable Counter Array
    • Figure 1.10. PCA Block Diagram
  • 1.6. Serial Ports
  • 1.7. 12-Bit Analog to Digital Converter
    • Figure 1.11. 12-Bit ADC Block Diagram
  • 1.8. 8-Bit Analog to Digital Converter
    • Figure 1.12. 8-Bit ADC Diagram
  • 1.9. Comparators and DACs
    • Figure 1.13. Comparator and DAC Diagram
• 2. ABSOLUTE MAXIMUM RATINGS
  • Table 2.1. Absolute Maximum Ratings*
• 3. GLOBAL DC ELECTRICAL CHARACTERISTICS
  • Table 1.1. Global DC Electrical Characteristics
• 4. PINOUT AND PACKAGE DEFINITIONS
  • Table 4.1. Pin Definitions
  • Figure 4.1. TQFP-100 Pinout Diagram
  • Figure 4.2. TQFP-100 Package Drawing
  • Figure 4.3. TQFP-64 Pinout Diagram
  • Figure 4.4. TQFP-64 Package Drawing
• 5. ADC0 (12-Bit ADC, C8051F020/1 Only)
  • Figure 5.1. 12-Bit ADC0 Functional Block Diagram
  • 5.1. Analog Multiplexer and PGA
    • Figure 5.2. Temperature Sensor Transfer Function
  • 5.2. ADC Modes of Operation
    • 5.2.1. Starting a Conversion
    • 5.2.2. Tracking Modes
    • Figure 5.3. 12-Bit ADC Track and Conversion Example Timing
    • 5.2.3. Settling Time Requirements
    • Figure 5.4. ADC0 Equivalent Input Circuits
    • Figure 5.5. AMX0CF: AMUX0 Configuration Register (C8051F020/1)
    • Figure 5.6. AMX0SL: AMUX0 Channel Select Register (C8051F020/1)
    • Figure 5.7. ADC0CF: ADC0 Configuration Register (C8051F020/1)
    • Figure 5.8. ADC0CN: ADC0 Control Register (C8051F020/1)
    • Figure 5.9. ADC0H: ADC0 Data Word MSB Register (C8051F020/1)
    • Figure 5.10. ADC0L: ADC0 Data Word LSB Register (C8051F020/1)
    • Figure 5.11. ADC0 Data Word Example (C8051F020/1)
  • 5.3. ADC0 Programmable Window Detector
    • Figure 5.12. ADC0GTH: ADC0 Greater-Than Data High Byte Register (C8051F020/1)
    • Figure 5.13. ADC0GTL: ADC0 Greater-Than Data Low Byte Register (C8051F020/1)
    • Figure 5.14. ADC0LTH: ADC0 Less-Than Data High Byte Register (C8051F020/1)
    • Figure 5.15. ADC0LTL: ADC0 Less-Than Data Low Byte Register (C8051F020/1)
    • Figure 5.16. 12-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data
    • Figure 5.17. 12-Bit ADC0 Window Interrupt Example: Right Justified Differential Data
    • Figure 5.18. 12-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data
    • Figure 5.19. 12-Bit ADC0 Window Interrupt Example: Left Justified Differential Data
    • Table 5.1. 12-Bit ADC0 Electrical Characteristics (C8051F020/1)
• 6. ADC0 (10-Bit ADC, C8051F022/3 Only)
  • Figure 6.1. 10-Bit ADC0 Functional Block Diagram
  • 6.1. Analog Multiplexer and PGA
    • Figure 6.2. Temperature Sensor Transfer Function
  • 6.2. ADC Modes of Operation
    • 6.2.1. Starting a Conversion
    • 6.2.2. Tracking Modes
    • Figure 6.3. 10-Bit ADC Track and Conversion Example Timing
    • 6.2.3. Settling Time Requirements
    • Figure 6.4. ADC0 Equivalent Input Circuits
    • Figure 6.5. AMX0CF: AMUX0 Configuration Register (C8051F022/3)
    • Figure 6.6. AMX0SL: AMUX0 Channel Select Register (C8051F022/3)
    • Figure 6.7. ADC0CF: ADC0 Configuration Register (C8051F022/3)
    • Figure 6.8. ADC0CN: ADC0 Control Register (C8051F022/3)
    • Figure 6.9. ADC0H: ADC0 Data Word MSB Register (C8051F022/3)
    • Figure 6.10. ADC0L: ADC0 Data Word LSB Register (C8051F022/3)
    • Figure 6.11. ADC0 Data Word Example (C8051F022/3)
  • 6.3. ADC0 Programmable Window Detector
    • Figure 6.12. ADC0GTH: ADC0 Greater-Than Data High Byte Register (C8051F022/3)
    • Figure 6.13. ADC0GTL: ADC0 Greater-Than Data Low Byte Register (C8051F022/3)
    • Figure 6.14. ADC0LTH: ADC0 Less-Than Data High Byte Register (C8051F022/3)
    • Figure 6.15. ADC0LTL: ADC0 Less-Than Data Low Byte Register (C8051F022/3)
    • Figure 6.16. 10-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data
    • Figure 6.17. 10-Bit ADC0 Window Interrupt Example: Right Justified Differential Data
    • Figure 6.18. 10-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data
    • Figure 6.19. 10-Bit ADC0 Window Interrupt Example: Left Justified Differential Data
    • Table 6.1. 10-Bit ADC0 Electrical Characteristics (C8051F022/3)
• 7. ADC1 (8-Bit ADC)
  • Figure 7.1. ADC1 Functional Block Diagram
  • 7.1. Analog Multiplexer and PGA
  • 7.2. ADC1 Modes of Operation
    • 7.2.1. Starting a Conversion
    • 7.2.2. Tracking Modes
    • Figure 7.2. ADC1 Track and Conversion Example Timing
    • 7.2.3. Settling Time Requirements
    • Figure 7.3. ADC1 Equivalent Input Circuit
    • Figure 7.4. ADC1CF: ADC1 Configuration Register (C8051F020/1/2/3)
    • Figure 7.5. AMX1SL: AMUX1 Channel Select Register (C8051F020/1/2/3)
    • Figure 7.6. ADC1CN: ADC1 Control Register (C8051F020/1/2/3)
    • Figure 7.7. ADC1: ADC1 Data Word Register
    • Figure 7.8. ADC1 Data Word Example
    • Table 7.1. ADC1 Electrical Characteristics
• 8. DACs, 12-BIT VOLTAGE MODE
  • Figure 8.1. DAC Functional Block Diagram
  • 8.1. DAC Output Scheduling
    • 8.1.1. Update Output On-Demand
    • 8.1.2. Update Output Based on Timer Overflow
  • 8.2. DAC Output Scaling/Justification
    • Figure 8.2. DAC0H: DAC0 High Byte Register
    • Figure 8.3. DAC0L: DAC0 Low Byte Register
    • Figure 8.4. DAC0CN: DAC0 Control Register
    • Figure 8.5. DAC1H: DAC1 High Byte Register
    • Figure 8.6. DAC1L: DAC1 Low Byte Register
    • Figure 8.7. DAC1CN: DAC1 Control Register
    • Table 8.1. DAC Electrical Characteristics
• 9. VOLTAGE REFERENCE (C8051F020/2)
  • Figure 9.1. Voltage Reference Functional Block Diagram
  • Figure 9.2. REF0CN: Reference Control Register
  • Table 9.1. Voltage Reference Electrical Characteristics
• 10. VOLTAGE REFERENCE (C8051F021/3)
  • Figure 10.1. Voltage Reference Functional Block Diagram
  • Figure 10.2. REF0CN: Reference Control Register
  • Table 10.1. Voltage Reference Electrical Characteristics
• 11. COMPARATORS
  • Figure 11.1. Comparator Functional Block Diagram
  • Figure 11.2. Comparator Hysteresis Plot
  • Figure 11.3. CPT0CN: Comparator0 Control Register
  • Figure 11.4. CPT1CN: Comparator1 Control Register
  • Table 11.1. Comparator Electrical Characteristics
• 12. CIP-51 MICROCONTROLLER
  • Figure 12.1. CIP-51 Block Diagram
  • 12.1. Instruction Set
    • 12.1.1. Instruction and CPU Timing
    • 12.1.2. MOVX Instruction and Program Memory
    • Table 12.1. CIP-51 Instruction Set Summary
  • 12.2. Memory Organization
    • Figure 12.2. Memory Map
    • 12.2.1. Program Memory
    • 12.2.2. Data Memory
    • 12.2.3. General Purpose Registers
    • 12.2.4. Bit Addressable Locations
    • 12.2.5. Stack
    • 12.2.6. Special Function Registers
    • Table 12.2. Special Function Register (SFR) Memory Map
    • Table 12.3. Special Function Registers
    • 12.2.7. Register Descriptions
    • Figure 12.3. SP: Stack Pointer
    • Figure 12.4. DPL: Data Pointer Low Byte
    • Figure 12.5. DPH: Data Pointer High Byte
    • Figure 12.6. PSW: Program Status Word
    • Figure 12.7. ACC: Accumulator
    • Figure 12.8. B: B Register
  • 12.3. Interrupt Handler
    • 12.3.1. MCU Interrupt Sources and Vectors
    • 12.3.2. External Interrupts
    • Table 12.4. Interrupt Summary
    • 12.3.3. Interrupt Priorities
    • 12.3.4. Interrupt Latency
    • 12.3.5. Interrupt Register Descriptions
    • Figure 12.9. IE: Interrupt Enable
    • Figure 12.10. IP: Interrupt Priority
    • Figure 12.11. EIE1: Extended Interrupt Enable 1
    • Figure 12.12. EIE2: Extended Interrupt Enable 2
    • Figure 12.13. EIP1: Extended Interrupt Priority 1
    • Figure 12.14. EIP2: Extended Interrupt Priority 2
  • 12.4. Power Management Modes
    • 12.4.1. Idle Mode
    • 12.4.2. Stop Mode
    • Figure 12.15. PCON: Power Control
• 13. RESET SOURCES
  • Figure 13.1. Reset Sources
  • 13.1. Power-on Reset
    • Figure 13.2. Reset Timing
  • 13.2. Power-fail Reset
  • 13.3. External Reset
  • 13.4. Software Forced Reset
  • 13.5. Missing Clock Detector Reset
  • 13.6. Comparator0 Reset
  • 13.7. External CNVSTR Pin Reset
  • 13.8. Watchdog Timer Reset
    • 13.8.1. Enable/Reset WDT
    • 13.8.2. Disable WDT
    • 13.8.3. Disable WDT Lockout
    • 13.8.4. Setting WDT Interval
    • Figure 13.3. WDTCN: Watchdog Timer Control Register
    • Figure 13.4. RSTSRC: Reset Source Register
    • Table 13.1. Reset Electrical Characteristics
• 14. OSCILLATORS
  • Figure 14.1. Oscillator Diagram
  • Figure 14.2. OSCICN: Internal Oscillator Control Register
  • Table 14.1. Internal Oscillator Electrical Characteristics
  • Figure 14.3. OSCXCN: External Oscillator Control Register
  • 14.1. External Crystal Example
  • 14.2. External RC Example
  • 14.3. External Capacitor Example
• 15. FLASH MEMORY
  • 15.1. Programming The FLASH Memory
    • Table 15.1. FLASH Electrical Characteristics
  • 15.2. Non-volatile Data Storage
  • 15.3. Security Options
    • Figure 15.1. FLASH Program Memory Map and Security Bytes
    • Figure 15.2. FLACL: FLASH Access Limit
    • Figure 15.3. FLSCL: FLASH Memory Control
    • Figure 15.4. PSCTL: Program Store Read/Write Control
• 16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM
  • 16.1. Accessing XRAM
    • 16.1.1. 16-Bit MOVX Example
    • 16.1.2. 8-Bit MOVX Example
  • 16.2. Configuring the External Memory Interface
  • 16.3. Port Selection and Configuration
    • Figure 16.1. EMI0CN: External Memory Interface Control
    • Figure 16.2. EMI0CF: External Memory Configuration
  • 16.4. Multiplexed and Non-multiplexed Selection
    • 16.4.1. Multiplexed Configuration
    • Figure 16.3. Multiplexed Configuration Example
    • 16.4.2. Non-multiplexed Configuration
    • Figure 16.4. Non-multiplexed Configuration Example
  • 16.5. Memory Mode Selection
    • Figure 16.5. EMIF Operating Modes
    • 16.5.1. Internal XRAM Only
    • 16.5.2. Split Mode without Bank Select
    • 16.5.3. Split Mode with Bank Select
    • 16.5.4. External Only
  • 16.6. Timing
    • Figure 16.6. EMI0TC: External Memory Timing Control
    • 16.6.1. Non-multiplexed Mode
    • Figure 16.7. Non-multiplexed 16-bit MOVX Timing
    • Figure 16.8. Non-multiplexed 8-bit MOVX without Bank Select Timing
    • Figure 16.9. Non-multiplexed 8-bit MOVX with Bank Select Timing
    • 16.6.2. Multiplexed Mode
    • Figure 16.10. Multiplexed 16-bit MOVX Timing
    • Figure 16.11. Multiplexed 8-bit MOVX without Bank Select Timing
    • Figure 16.12. Multiplexed 8-bit MOVX with Bank Select Timing
    • Table 16.1. AC Parameters for External Memory Interface
• 17. PORT INPUT/OUTPUT
  • Figure 17.1. Port I/O Cell Block Diagram
  • Table 17.1. Port I/O DC Electrical Characteristics
  • Figure 17.2. Lower Port I/O Functional Block Diagram
  • 17.1. Ports 0 through 3 and the Priority Crossbar Decoder
    • Figure 17.3. Priority Crossbar Decode Table
    • 17.1.1. Crossbar Pin Assignment and Allocation
    • 17.1.2. Configuring the Output Modes of the Port Pins
    • 17.1.3. Configuring Port Pins as Digital Inputs
    • 17.1.4. External Interrupts (IE6 and IE7)
    • 17.1.5. Weak Pull-ups
    • 17.1.6. Configuring Port 1 Pins as Analog Inputs (AIN1.[7:0])
    • 17.1.7. External Memory Interface Pin Assignments
    • Figure 17.4. Priority Crossbar Decode Table
    • Figure 17.5. Priority Crossbar Decode Table
    • 17.1.8. Crossbar Pin Assignment Example
    • Figure 17.6. Crossbar Example:
    • Figure 17.7. XBR0: Port I/O Crossbar Register 0
    • Figure 17.8. XBR1: Port I/O Crossbar Register 1
    • Figure 17.9. XBR2: Port I/O Crossbar Register 2
    • Figure 17.10. P0: Port0 Data Register
    • Figure 17.11. P0MDOUT: Port0 Output Mode Register
    • Figure 17.12. P1: Port1 Data Register
    • Figure 17.13. P1MDIN: Port1 Input Mode Register
    • Figure 17.14. P1MDOUT: Port1 Output Mode Register
    • Figure 17.15. P2: Port2 Data Register
    • Figure 17.16. P2MDOUT: Port2 Output Mode Register
    • Figure 17.17. P3: Port3 Data Register
    • Figure 17.18. P3MDOUT: Port3 Output Mode Register
    • Figure 17.19. P3IF: Port3 Interrupt Flag Register
  • 17.2. Ports 4 through 7 (C8051F020/2 only)
    • 17.2.1. Configuring Ports which are not Pinned Out
    • 17.2.2. Configuring the Output Modes of the Port Pins
    • 17.2.3. Configuring Port Pins as Digital Inputs
    • 17.2.4. Weak Pull-ups
    • 17.2.5. External Memory Interface
    • Figure 17.20. P74OUT: Ports 7 - 4 Output Mode Register
    • Figure 17.21. P4: Port4 Data Register
    • Figure 17.22. P5: Port5 Data Register
    • Figure 17.23. P6: Port6 Data Register
    • Figure 17.24. P7: Port7 Data Register
• 18. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0)
  • Figure 18.1. SMBus0 Block Diagram
  • Figure 18.2. Typical SMBus Configuration
  • 18.1. Supporting Documents
  • 18.2. SMBus Protocol
    • Figure 18.3. SMBus Transaction
    • 18.2.1. Arbitration
    • 18.2.2. Clock Low Extension
    • 18.2.3. SCL Low Timeout
    • 18.2.4. SCL High (SMBus Free) Timeout
  • 18.3. SMBus Transfer Modes
    • 18.3.1. Master Transmitter Mode
    • Figure 18.4. Typical Master Transmitter Sequence
    • 18.3.2. Master Receiver Mode
    • Figure 18.5. Typical Master Receiver Sequence
    • 18.3.3. Slave Transmitter Mode
    • Figure 18.6. Typical Slave Transmitter Sequence
    • 18.3.4. Slave Receiver Mode
    • Figure 18.7. Typical Slave Receiver Sequence
  • 18.4. SMBus Special Function Registers
    • 18.4.1. Control Register
    • Figure 18.8. SMB0CN: SMBus0 Control Register
    • 18.4.2. Clock Rate Register
    • Figure 18.9. SMB0CR: SMBus0 Clock Rate Register
    • 18.4.3. Data Register
    • Figure 18.10. SMB0DAT: SMBus0 Data Register
    • 18.4.4. Address Register
    • Figure 18.11. SMB0ADR: SMBus0 Address Register
    • 18.4.5. Status Register
    • Figure 18.12. SMB0STA: SMBus0 Status Register
    • Table 18.1. SMB0STA Status Codes and States
• 19. SERIAL PERIPHERAL INTERFACE BUS (SPI0)
  • Figure 19.1. SPI Block Diagram
  • 19.1. Signal Descriptions
    • 19.1.1. Master Out, Slave In (MOSI)
    • 19.1.2. Master In, Slave Out (MISO)
    • 19.1.3. Serial Clock (SCK)
    • 19.1.4. Slave Select (NSS)
    • Figure 19.2. Typical SPI Interconnection
  • 19.2. SPI0 Operation
    • Figure 19.3. Full Duplex Operation
  • 19.3. Serial Clock Timing
    • Figure 19.4. Data/Clock Timing Diagram
  • 19.4. SPI Special Function Registers
    • Figure 19.5. SPI0CFG: SPI0 Configuration Register
    • Figure 19.6. SPI0CN: SPI0 Control Register
    • Figure 19.7. SPI0CKR: SPI0 Clock Rate Register
    • Figure 19.8. SPI0DAT: SPI0 Data Register
• 20. UART0
  • Figure 20.1. UART0 Block Diagram
  • 20.1. UART0 Operational Modes
    • Table 20.1. UART0 Modes
    • 20.1.1. Mode 0: Synchronous Mode
    • Figure 20.2. UART0 Mode 0 Interconnect
    • Figure 20.3. UART0 Mode 0 Timing Diagram
    • 20.1.2. Mode 1: 8-Bit UART, Variable Baud Rate
    • Figure 20.4. UART0 Mode 1 Timing Diagram
    • 20.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate
    • Figure 20.5. UART Modes 2 and 3 Timing Diagram
    • 20.1.4. Mode 3: 9-Bit UART, Variable Baud Rate
    • Figure 20.6. UART Modes 1, 2, and 3 Interconnect Diagram
  • 20.2. Multiprocessor Communications
    • Figure 20.7. UART Multi-Processor Mode Interconnect Diagram
  • 20.3. Frame and Transmission Error Detection
    • Table 20.2. Oscillator Frequencies for Standard Baud Rates
    • Figure 20.8. SCON0: UART0 Control Register
    • Figure 20.9. SBUF0: UART0 Data Buffer Register
    • Figure 20.10. SADDR0: UART0 Slave Address Register
    • Figure 20.11. SADEN0: UART0 Slave Address Enable Register
• 21. UART1
  • Figure 21.1. UART1 Block Diagram
  • 21.1. UART1 Operational Modes
    • Table 21.1. UART1 Modes
    • 21.1.1. Mode 0: Synchronous Mode
    • Figure 21.2. UART1 Mode 0 Interconnect
    • Figure 21.3. UART1 Mode 0 Timing Diagram
    • 21.1.2. Mode 1: 8-Bit UART, Variable Baud Rate
    • Figure 21.4. UART1 Mode 1 Timing Diagram
    • 21.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate
    • Figure 21.5. UART Modes 2 and 3 Timing Diagram
    • 21.1.4. Mode 3: 9-Bit UART, Variable Baud Rate
    • Figure 21.6. UART Modes 1, 2, and 3 Interconnect Diagram
  • 21.2. Multiprocessor Communications
    • Figure 21.7. UART Multi-Processor Mode Interconnect Diagram
  • 21.3. Frame and Transmission Error Detection
    • Table 21.2. Oscillator Frequencies for Standard Baud Rates
    • Figure 21.8. SCON1: UART1 Control Register
    • Figure 21.9. SBUF1: UART1 Data Buffer Register
    • Figure 21.10. SADDR1: UART1 Slave Address Register
    • Figure 21.11. SADEN1: UART1 Slave Address Enable Register
• 22. TIMERS
  • Figure 22.1. CKCON: Clock Control Register
  • 22.1. Timer 0 and Timer 1
    • 22.1.1. Mode 0: 13-bit Counter/Timer
    • Figure 22.2. T0 Mode 0 Block Diagram
    • 22.1.2. Mode 1: 16-bit Counter/Timer
    • 22.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
    • Figure 22.3. T0 Mode 2 (8-bit Auto-Reload) Block Diagram
    • 22.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
    • Figure 22.4. T0 Mode 3 (Two 8-bit Timers) Block Diagram
    • Figure 22.5. TCON: Timer Control Register
    • Figure 22.6. TMOD: Timer Mode Register
    • Figure 22.7. TL0: Timer 0 Low Byte
    • Figure 22.8. TL1: Timer 1 Low Byte
    • Figure 22.9. TH0 Timer 0 High Byte
    • Figure 22.10. TH1: Timer 1 High Byte
  • 22.1. Timer 2
    • 22.1.1. Mode 0: 16-bit Counter/Timer with Capture
    • Figure 22.11. T2 Mode 0 Block Diagram
    • 22.1.2. Mode 1: 16-bit Counter/Timer with Auto-Reload
    • Figure 22.12. T2 Mode 1 Block Diagram
    • 22.1.3. Mode 2: Baud Rate Generator
    • Figure 22.13. T2 Mode 2 Block Diagram
    • Figure 22.14. T2CON: Timer 2 Control Register
    • Figure 22.15. RCAP2L: Timer 2 Capture Register Low Byte
    • Figure 22.16. RCAP2H: Timer 2 Capture Register High Byte
    • Figure 22.17. TL2: Timer 2 Low Byte
    • Figure 22.18. TH2 Timer 2 High Byte
  • 22.2. Timer 3
    • Figure 22.19. Timer 3 Block Diagram
    • Figure 22.20. TMR3CN: Timer 3 Control Register
    • Figure 22.21. TMR3RLL: Timer 3 Reload Register Low Byte
    • Figure 22.22. TMR3RLH: Timer 3 Reload Register High Byte
    • Figure 22.23. TMR3L: Timer 3 Low Byte
    • Figure 22.24. TMR3H: Timer 3 High Byte
  • 22.3. Timer 4
    • 22.3.1. Mode 0: 16-bit Counter/Timer with Capture
    • Figure 22.25. T4 Mode 0 Block Diagram
    • 22.3.2. Mode 1: 16-bit Counter/Timer with Auto-Reload
    • Figure 22.26. T4 Mode 1 Block Diagram
    • 22.3.3. Mode 2: Baud Rate Generator
    • Figure 22.27. T4 Mode 2 Block Diagram
    • Figure 22.28. T4CON: Timer 4 Control Register
    • Figure 22.29. RCAP4L: Timer 4 Capture Register Low Byte
    • Figure 22.30. RCAP4H: Timer 4 Capture Register High Byte
    • Figure 22.31. TL4: Timer 4 Low Byte
    • Figure 22.32. TH4 Timer 4 High Byte
• 23. PROGRAMMABLE COUNTER ARRAY
  • Figure 23.1. PCA Block Diagram
  • 23.1. PCA Counter/Timer
    • Table 23.1. PCA Timebase Input Options
    • Figure 23.2. PCA Counter/Timer Block Diagram
  • 23.2. Capture/Compare Modules
    • Figure 23.3. PCA Interrupt Block Diagram
    • Table 23.2. PCA0CPM Register Settings for PCA Capture/Compare Modules
    • 23.2.1. Edge-triggered Capture Mode
    • Figure 23.4. PCA Capture Mode Diagram
    • 23.2.2. Software Timer (Compare) Mode
    • Figure 23.5. PCA Software Timer Mode Diagram
    • 23.2.3. High Speed Output Mode
    • Figure 23.6. PCA High Speed Output Mode Diagram
    • 23.2.4. Frequency Output Mode
    • Figure 23.7. PCA Frequency Output Mode
    • 23.2.5. 8-Bit Pulse Width Modulator Mode
    • Figure 23.8. PCA 8-Bit PWM Mode Diagram
    • 23.2.6. 16-Bit Pulse Width Modulator Mode
    • Figure 23.9. PCA 16-Bit PWM Mode
  • 23.3. Register Descriptions for PCA0
    • Figure 23.10. PCA0CN: PCA Control Register
    • Figure 23.11. PCA0MD: PCA0 Mode Register
    • Figure 23.12. PCA0CPMn: PCA0 Capture/Compare Mode Registers
    • Figure 23.13. PCA0L: PCA0 Counter/Timer Low Byte
    • Figure 23.14. PCA0H: PCA0 Counter/Timer High Byte
    • Figure 23.15. PCA0CPLn: PCA0 Capture Module Low Byte
    • Figure 23.16. PCA0CPHn: PCA0 Capture Module High Byte
• 24. JTAG (IEEE 1149.1)
  • Figure 24.1. IR: JTAG Instruction Register
  • 24.1. Boundary Scan
    • Table 24.1. Boundary Data Register Bit Definitions
    • 24.1.1. EXTEST Instruction
    • 24.1.2. SAMPLE Instruction
    • 24.1.3. BYPASS Instruction
    • 24.1.4. IDCODE Instruction
    • Figure 24.2. DEVICEID: JTAG Device ID Register
  • 24.2. Flash Programming Commands
    • Figure 24.3. FLASHCON: JTAG Flash Control Register
    • Figure 24.4. FLASHADR: JTAG Flash Address Register
    • Figure 24.5. FLASHDAT: JTAG Flash Data Register
  • 24.3. Debug Support