Description
Package
Schematic Symbol
Features
Absolute Maximum Ratings
SYMBOL
VALUE
UNITS
Peak Off-State Voltage
V
DRM
2000
V
Peak Reverse Voltage
V
RRM
-5
V
Off-State Rate of Change of Voltage Immunity
dv/dt
1000
V/uSec
Continuous Anode Current at 110
o
C
I
A110
20
A
Repetitive Peak Anode Current (Pulse Width=1uSec)
I
ASM
2000
A
Nonrepetitive Peak Anode Current (Pulse Width=250nSec)
I
ASM
4000
A
Rate of Change of Current
dI/dt
20
kA/uSec
Continuous Gate-Cathode Voltage
V
GKS
+/-20
V
Peak Gate-Cathode Voltage
V
GKM
+/-25
V
Minimum Negative Gate-Cathode Voltage Required for Garanteed Off-State
V
GK(OFF-MIN)
-5
V
Maximum Junction Temperature
T
JM
150
o
C
Maximum Soldering Temperature (Installation)
260
o
C
This SILICON POWER product is protected by one or more of the following U.S. Patents:
ThinPak
TM
Gate Bond Area
Gate Return
Bond Area
Anode
Bond Area
Opposite side
Cathode Bond Area
5,446,316
5,557,656
5,564,226
5,517,058
4,814,283
5,135,890
5,521,436
5,585,310
5,248,901
5,366,932
5,497,013
5,532,635
5,105,536
5,777,346
5,446,316
5,577,656
5,473,193
5,166,773
5,209,390
5,139,972
5,103,290
5,028,987
5,304,847
5,569,957
4,958,211
5,111,268
5,260,590
5,350,935
5,640,300
5,184,206
5,206,186
5,757,036
5,777,346
5,995,349
4,801,985
4,476,671
4,857,983
4,888,627
4,912,541
5,424,563
5,399,892
5,468,668
5,082,795
4,980,741
4,941,026
4,927,772
4,739,387
4,648,174
4,644,637
4,374,389
4,750,666
4,429,011
5,293,070
This voltage controlled Solidtron (VCS) discharge switch utilizes
an n-type MOS-Controlled Thyristor mounted on a ThinPak
TM
,
ceramic "chip-scale" hybrid.
The VCS features the high peak current capability and low On-
state voltage drop common to SCR thyristors combined with
extremely high dI/dt capability. This semiconductor is intended
for the control of high power circuits with the use of very small
amounts of input energy and is ideally suited for capacitor
discharge applications.
The ThinPak
TM
Package is a perforated, metalized ceramic
substrate attached to the silicon using 302
o
C solder. An epoxy
underfill is applied to protect the high voltage termination from
debris. All exterior metal surfaces are tinned with 63pb/37sn
solder providing the user with a circuit ready part. It's small size
and low profile make it extremely attractive to high dI/dt
applications where stray series inductance must be kept to a
minimum.
l
2000V Peak Off-State Voltage
l
20A Continuous Rating
l
4kA Surge Current Capability
l
High dI/dt Capability
l
Low On-State Voltage
l
MOS Gated Control
l
Low Inductance Package
Anode (A)
Gate (G)
Cathode (K)
Gate Return (GR)
Preliminary Data Sheet - Product Status : First Production : This data sheet contains preliminary data . Supplementary data will be
published at a later date. Silicon Power reserves the right to make changes at any time without notice.
Advanced Pulse Power Device
N-MOS VCS, ThinPak
TM
Preliminary Data Sheet
SMCT TA20N20A10
Performance Characteristics
T
J
=25
o
C unless otherwise specified
Measurements
Parameters
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Anode to Cathode Breakdown Voltage
V
(BR)
V
GK
=-5, I
A
=1mA
2000
V
Anode-Cathode Off-State Current
i
D
V
GK
=-5V, V
AK
=2000V
T
C
=25
o
C
<10
100
uA
T
C
=150
o
C
250
1000
uA
Gate-Cathode Turn-On Threshold Voltage
V
GK(TH)
V
AK
=V
GK
, I
AK
=1mA
0.7
V
Gate-Cathode Leakage Current
I
GK(lkg)
V
GK
=+/-20V
500
nA
Anode-Cathode On-State Voltage
V
T
I
T
=25A, V
GK
=+5V
T
C
=25
o
C
2.4
3.0
V
T
C
=150
o
C
3
3.5
V
Input Capacitance
C
ISS
5
nF
Turn-on Delay Time
t
D(ON)
0.2uF Capacitor Discharge
230
300
nS
Rate of Change of Current
dI/dt
T
J
=25
o
C, V
GK
= -5V to +5V
18
kA/uSec
Peak Anode Current
I
P
V
AK
=1400V, RG=4.7
2200
A
Discharge Event Energy
E
DIS
L
S
= 15nH
196
mJ
Turn-on Delay Time
t
D(ON)
0.2uF Capacitor Discharge
180
250
nS
Rate of Change of Current
dI/dt
T
J
=25
o
C, V
GK
= -5V to +5V
28
kA/uSec
Peak Anode Current
I
P
V
AK
=1800V, RG=4.7
3300
A
Discharge Event Energy
E
DIS
L
S
= 15nH
310
mJ
Junction to Case Thermal Resistance
R
JC
Anode (bottom) side cooled (Note 1.)
0.09
o
C/W
Junction to Case Thermal Resistance
R
JC
Cathode-Gate (top) side cooled (Note 2.)
1.6
o
C/W
Notes:
1. Case Exterior Assumed to be 0.002" of 63sn/37pb solder applied directly to Anode.
2. Case Exterior Assummed to be 0.002" of 63sn/37pb solder applied directly to cathode bond area of thinPak.
Typical Performance Curves
(unless otherwise specified)
Typical Performance Curves
Figure 1. On-State Characteristics
Figure 2. On-State Characteristics
Figure 3. Predicted High Current On-State Characteristics
0
25
50
75
100
125
150
0.0
2.0
4.0
6.0
8.0
10.0
V
T
- On-State Voltage=Volts
I
T
- On-State Current-A
V
GK
=+5V
Pulse Duration = 250uSec.
Duty Cycle=<0.5%
T
J
=25
o
C
T
J
=150
o
C
T
J
=85
o
C
0
5
10
15
20
25
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
T
- On-State Voltage=Volts
I
T
- On-State Current-A
V
GK
=+5V
Pulse Duration = 250uSec.
Duty Cycle=<0.5%
T
J
=25
o
C
T
J
=150
o
C
T
J
=85
o
C
0
500
1000
1500
2000
2500
3000
3500
4000
0
20
40
60
80
100
120
140
160
180
200
220
V
T
- On-State Voltage - V
I
T
- On-State Current-A
T
J
=25
o
C
R
ON
= 30m
T
J
=150
o
C
R
ON
= 54m
T
J
=85
o
C
R
ON
= 39m
Advanced Pulse Power Device
N-MOS VCS, ThinPak
TM
Preliminary Data Sheet
SMCT TA20N20A10
Typical Performance Curves
(Continued)
Figure 7. 0.2uF Pulsed Discharge Circuit and Waveforms
Application Notes
Packaging and Handling
Figure 8. Package Dimensions
A1. Use of Gate Return Bond Area.
The VCS was designed for high di/dt applications. An independent cathode connection or "Gate Return Bond Area" was
provided to minimize the effects of rapidly changing Anode-Cathode current on the Gate control voltage, (V=L*di/dt). It is
therefore, critcal that the user utilize the Gate Return Bond Area as the point at which the gate driver reference (return) is
attached to the VCS device.
1. All metal surfaces are tinned using 63pb/37sn
solder.
2. Installation reflow temperature should not exceed
260
o
C or internal package degradation may result.
3. Package may be cooled from either top or bottom.
4. As with all MOS gated devices, proper handling
procedures must be observed to prevent electrostatic
discharge which may result in permanent damage to
the gate of the device
V
GK
V
AK
I
A
I
P
T
D(ON)
0 Ref.
0 Ref.
90%
10%
dI/dt - 10% to 50% of I
A
l
The waveform shown is representative
of one produced using a very low
inductance circuit (<10nH) and a
SMCTTA32N14A10 MCT. SMCT
TA20N20A10 devices do not produce
ringing waveforms
l
V
GK
is held positive until I
A
oscillations
have ended ( I
A
=0).
Supply
Voltage
L
SERIES (TOTAL)
DUT
R
SENSE
= 0.010
C=0.2uF +
-
R
G
Gate
Driver
+5V
-5V
l
L
SERIES(TOTAL)
is caculated using
1 / (f 2
)
2
C
where f = frequency of I
A
when using
SMCT TA32N14A10 for circuit set up
and calibration.
l
R
SENSE
is a calibrated
Current Viewing Resistor (CVR)
.042 Thick
Advanced Pulse Power Device
N-MOS VCS, ThinPak
TM
Preliminary Data Sheet
SMCT TA20N20A10
PDF 
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