1
Rev. 7/15/03
SP6123 Low Voltage, 8 Pin, Synchronous Buck Controller Copyright 2003 Sipex Corporation
SP6123
Optimized for Single Supply, 3V - 5.5V Applications
High Efficiency: Greater Than 95% Possible
Accurate Fixed 300kHz (SP6123) or
500kHz (SP6123A) Frequency Operation
Fast Transient Response
Internal Soft Start Circuit
Accurate 0.8V Reference Allows Low Output
Voltages
Resistor Programmable Output Voltage
Loss-less Current Limit with High Side R
DS(ON)
Sensing
Hiccup Mode Current Limit Protection
Dual N-Channel MOSFET Synchronous Driver
Quiescent Current: 500
A, 30
A in Shutdown
8-Pin Surface Mount Package
Low Voltage, 8 Pin, Synchronous Buck Controller
Ideal for 2A to 10A, Small Footprint, DC-DC Power Converters
APPLICATIONS
DSP
Microprocessor Core
I/O & Logic
Industrial Control
Distributed Power
Low Voltage Power
DESCRIPTION
The SP6123 is a fixed frequency, voltage mode, synchronous PWM controller designed to
work from a single 5V or 3.3V input supply, providing excellent AC and DC regulation for high
efficiency power conversion. Requiring only few external components, the SP6123 pack-
aged in an 8-pin SOIC, is especially suited for low voltage applications where cost, small size
and high efficiency are critical. The operating frequency is internally set to 300kHz (SP6123)
or 500kHz (SP6123A), allowing small inductor values and minimizing PC board space. The
SP6123 drives a dual N-channel synchronous power MOSFET stage for improved efficiency
and includes an accurate 0.8V reference for low output voltage applications.
TYPICAL APPLICATION CIRCUIT
BST
SWN
V
CC
V
FB
COMP
GH
GL
GND
CC
4.7nF
RZ
15k
CB
2.2F
V
IN
SP6123
CP
56pF
FDS6890A
C
IN
680F
R1
10k
V
OUT
IN
3V to 5.5V
0.8V to 5.0V
2A to 10A
(1.6V, 4A shown)
CBST
1F
MBR0530
L1
1.5H
FDS6890A
C
OUT1
470F
C
OUT3
1F
R2
10k
C
OUT2
470F
STPS2L25U
1
2
3
4
5
6
7
8
COMP
GL
BST
GH
SWN
V
FB
V
CC
SP6123
8 Pin SOIC
GND
FEATURES
2
Rev. 7/15/03
SP6123 Low Voltage, 8 Pin, Synchronous Buck Controller Copyright 2003 Sipex Corporation
PARAMETER
MIN
TYP MAX
UNITS
CONDITIONS
QUIESCENT CURRENT
V
CC
Supply Current
0.5
1.0
mA
No Switching
V
CC
Supply Current (Disabled)
30
60
A
COMP = 0V
ERROR AMPLIFIER
Error Amplifier Transconductance
0.6
mS
COMP Sink Current
10
35
65
A
V
FB
= 0.9V, COMP = 0.9V, No Faults
COMP Source Current
10
35
65
A
V
FB
= 0.7V, COMP = 2V
COMP Output Impedance
3
M
V
FB
Input Bias Current
50
130
nA
Error Amplifier Reference
0.788 0.8
0.812
V
Trimmed with Error Amp in Unity Gain
OSCILLATOR & DELAY PATH
Internal Oscillator Frequency
270
300
330
kHz
SP6123
Internal Oscillator Frequency
450
500
550
kHz
SP6123A
Max. Controlled Duty Cycle
93
%
Loop in control - 100% DC Possible
Minimum Duty Cycle
0
%
Comp=0.7V
Minimum GH Pulse Width
100
250
ns
V
CC
> 4.5V, Ramp up COMP voltage until
GH starts switching
CURRENT LIMIT
Internal Current Limit Threshold
160
200
240
mV
V
CC
- V
SWN
; Temp = 25
C;
V
BST
- V
CC
> 2.5V
Current Limit Threshold
0.34
%/C
Temperature Coefficient
Current Limit Time Constant
15
us
SOFT START, SHUTDOWN, UVLO
Internal Soft Start Slew Rate
SP6123A
0.35 0.60
0.95
V/ms
V
FB
= 0.7V and 0V, measure hiccup cycle
SP6123
0.1
0.3
0.6
V/ms
period
COMP Discharge Current
185
A
COMP = 0.5V, Fault Initiated
COMP Clamp Voltage
0.55 0.65
0.75
V
V
FB
= 0.9V
COMP Clamp Current
10
30
65
A
COMP = 0.5V, V
FB
= 0.9V
Shutdown Threshold Voltage
0.29 0.34
0.39
V
Measured at COMP Pin
Shutdown Input Pull-up Current
2
5
10
A
COMP = 0.2V, Measured at COMP pin
V
CC
Start Threshold
2.63
2.8
2.95
V
V
CC
Stop Threshold
2.47
2.7
2.9
V
ELECTRICAL CHARACTERISTICS
Unless otherwise specified: 0
C < T
A
< 70
C, 3.0V < V
CC
< 5.5V, C
COMP
= 22nF, CGH = CGL = 3.3nF, V
FB
= 0.8V,
SWN = GND=0V, typical value for design guideline only.
V
CC .......................................................................................................
7V
BST .................................................................. 13.2V
BST-SWN .............................................................. 7V
All other pins ................................ -0.3V to V
CC
+ 0.3V
Peak Output Current < 10
s
GH,GL .................................................................. 2A
Storage Temperature ........................ -65
C to 150
C
Power Dissipation ................................................. 1W
Lead Temperature (Soldering, 10 sec) ............ 300
C
Thermal Resistance
JC
.............................. 38.8
C/W
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may
affect reliability.
ABSOLUTE MAXIMUM RATINGS
3
Rev. 7/15/03
SP6123 Low Voltage, 8 Pin, Synchronous Buck Controller Copyright 2003 Sipex Corporation
PIN DESCRIPTION
PIN N0. PIN NAME DESCRIPTION
1
GL
High current driver output for the low side MOSFET switch. It is always low if GH is high.
GL swings from GND to V
CC
.
2
V
CC
Positive input supply for the control circuitry and the low side gate driver. Properly bypass
this pin to GND with a low ESL/ESR ceramic capacitor.
3
GND
Ground pin. Both power and control circuitry of the IC is referenced to this pin.
4
COMP
Output of the Error Amplifier. It is internally connected to the inverting input of the PWM
comparator. A lead-lag network is typically connected to the COMP pin to compensate the
feedback loop in order to optimize the dynamic performance of the voltage mode control
loop. Sleep mode can be invoked by pulling the COMP pin below 0.3V with an external
open-drain transistor. Supply current is reduced to 30
A (typical) in shutdown. An internal
5
A pull-up ensures start-up.
5
V
FB
Feedback Voltage Pin. It is the inverting input of the Error Amplifier and serves as the
output voltage feedback point for the Buck converter. The output voltage is sensed and
can be adjusted through an external resistor divider.
6
SWN
Lower supply rail for the GH high-side gate driver. It also connects to the Current Limit
comparator. Connect this pin to the switching node at the junction between the two
external power MOSFET transistors. This pin monitors the voltage drop across the R
DS(ON)
of the high side N-channel MOSFET while it is conducting. When this drop exceeds the
internal 200mV threshold, the overcurrent comparator sets the fault latch and terminates
the output pulses. The controller stops switching and goes through a hiccup sequence. This
prevents excessive power dissipation in the external power MOSFETS during an overload
condition. An internal delay circuit prevents that very short and mild overload conditions,
that could occur during a load transient, from activating the current limit circuit.
7
GH
High current driver output for the high side MOSFET switch. It is always low if GL is high or
during a fault. GH swings from SWN to BST.
8
BST
High side driver supply pin. Connect BST to the external boost diode and capacitor as
shown in the application schematic of page #1. Voltage between BST and SWN should
not exceed 7V.
ELECTRICAL CHARACTERISTICS: Continued
Unless otherwise specified: 0
C < T
A
< 70
C, 3.0V < V
CC
< 5.5V, C
COMP
= 22nF, CGH = CGL = 3.3nF, V
FB
= 0.8V,
SWN = GND=0V, typical value for design guideline only.
PARAMETER
MIN TYP
MAX
UNITS
CONDITIONS
GATE DRIVERS
GH Rise Time
60
110
ns
V
CC
> 4.5V
GH Fall Time
60
110
ns
V
CC
> 4.5V
GL Rise Time
60
110
ns
V
CC
> 4.5V
GL Fall Time
60
110
ns
V
CC
> 4.5V
GH to GL Non-Overlap Time
0
100
140
ns
V
CC
> 4.5V, measured at 2 Volt Threshold
GL to GH Non-Overlap Time
0
100
140
ns
V
CC
> 4.5V, measured at 2 Volt Threshold
4
Rev. 7/15/03
SP6123 Low Voltage, 8 Pin, Synchronous Buck Controller Copyright 2003 Sipex Corporation
General Overview
The SP6123 is a constant frequency, voltage mode,
synchronous PWM controller designed for low
voltage, DC/DC step down converters. It is in-
tended to provide complete control for a high
power, high efficiency, precisely regulated output
voltage from a highly integrated 8-pin solution.
The internal free-running oscillator accurately sets
the PWM frequency at 300kHz or 500kHz without
requiring any external elements and allows the use
of physically small, low value external compo-
nents without compromising performance. A
transconductance amplifier is used for the error
amplifier, which compares an attenuated sample
of the output voltage with a precision, 0.8V refer-
ence voltage. The output of the error amplifier
(COMP), is compared to a 0.75V peak-to-peak
ramp waveform to provide PWM control. The
COMP pin provides access to the output of the
error amplifier and allows the use of external
components to stabilize the voltage loop.
High efficiency is obtained through the use of
synchronous rectification. Synchronous regula-
tors replace the catch diode in the standard buck
converter with a low R
DS(ON)
N-channel
MOSFET switch allowing for significant effi-
ciency improvements. The SP6123 includes two
fast MOSFET drivers with internal non-overlap
circuitry and drives a pair of N-channel power
transistors. The SP6123 includes an internal
soft-start circuit that provides controlled ramp
up of the output voltage, preventing overshoot
and inrush current at power up.
Current limiting is implemented by monitoring
the voltage drop across the R
DS(ON)
of the high
side N-channel MOSFET while it is conducting,
thereby eliminating the need for an external
sense resistor. The overcurrent comparator has
a built-in threshold of 200mV.
When the overcurrent threshold is exceeded, the
overcurrent comparator sets the fault latch and
terminates the output pulses. The controller
stops switching and goes through a hiccup se-
quence. This prevents excessive power dissipa-
tion in the external power MOSFETs during an
overload condition. An internal delay circuit
prevents that very short and mild overload con-
ditions, that could occur during a load transient,
activate the current limit circuit.
+
-
-
+
-
+
Synchronous
Driver
PWM
Logic
S
Q
R
Reset
Dominant
R
Q
S
V
CC
SWN
Reference
4
5
0.8V
UVLO
FAULT
SWN
6
1
GL
7
DRIVER ENABLE
RESET
Dominant
PWM COMP
FAULT
+
-
X 2.5
GH
GH
5
A
340mV
SHUTDOWN
GM
ERROR
AMP
Over Current
(Gated S&H)
2.8V ON
2.7V OFF
COMP
SHUTDOWN
F = 300kHz; SP6123
F = 500kHz; SP6123A
750mV RAMP
SOFTSTART
V
FB
COMP
2
-
+
-
+
1V
500mV
(3400 ppm/
C)
+
-
GND
3
8
BST
FUNCTIONAL DIAGRAM
THEORY OF OPERATION
5
Rev. 7/15/03
SP6123 Low Voltage, 8 Pin, Synchronous Buck Controller Copyright 2003 Sipex Corporation
A low power sleep mode can be invoked in the
SP6123 by externally forcing the COMP pin
below 0.3V. Quiescent supply current in sleep
mode is typically less than 30
A. An internal
5
A pull-up current at the COMP pin brings the
SP6123 out of shutdown mode.
An internal 0.8V 1.5% reference allows output
voltage adjustment for low voltage applications.
The SP6123 also includes an accurate under-
voltage lockout that shuts down the controller
when the input voltage falls below 2.7V. Output
overvoltage protection is achieved by turning
off the high side switch and turning on the low
side N-channel MOSFET 100% of the time.
Enable
Low quiescent mode or "Sleep Mode" is initi-
ated by pulling the COMP pin below 0.3V with
an external open-drain transistor. Supply cur-
rent is reduced to 30
A (typical) in shutdown.
On power-up, assuming that VCC has exceeded
the UVLO start threshold (2.8V), an internal
5
A pull-up current at the COMP pin brings the
SP6123 out of shutdown mode and ensures
start-up. During normal operating conditions
and in absence of a fault, an internal clamp
prevents the COMP pin from swinging below
0.6V. This guarantees that during mild transient
conditions, due either to line or load variations,
the SP6123 does not enter shutdown unless it is
externally activated.
During Sleep Mode, the high side and low side
MOSFETS are turned off and the internal soft
start voltage is held low.
UVLO
Assuming that there is no shutdown condition
present, then the voltage on the V
CC
pin deter-
mines operation of the SP6123. As V
CC
rises,
the UVLO block monitors V
CC
and keeps the
high side and low side MOSFETS off and the
internal SS voltage low until V
CC
reaches 2.8V.
If no faults are present, the SP6123 will initiate
a soft start when V
CC
exceeds 2.8 V.
Hysteresis (about 100mV) in the UVLO com-
parator provides noise immunity at start-up.
Soft Start
Soft start is required on step-down controllers to
prevent excess inrush current through the power
train during start-up. Typically this is managed
by sourcing a controlled current into a timing
capacitor and then using the voltage across this
capacitor to slowly ramp up either the error amp
reference or the error amp output (COMP). The
control loop creates narrow width driver pulses
while the output voltage is low and allows these
pulses to increase to their steady-state duty
cycle as the output voltage increases to its regu-
lated value. As a result of controlling the induc-
tor volt*second product during startup, inrush
current is also controlled.
In the SP6123 the duration of the soft-start is
controlled by an internal timing circuit that
provides a 0.3V/ms slew-rate, which is used
during startup and overcurrent to set the hiccup
time. The SP6123 implements soft-start by ramp-
ing up the error amplifier reference voltage
providing a controlled slew-rate of the output
voltage, thereby preventing overshoot and in-
rush current at power up.
The presence of the output capacitor creates
extra current draw during startup. Simply stated,
dV
OUT
/dt requires an average sustained current
in the output capacitor and this current must be
considered while calculating peak inrush cur-
rent and over current thresholds. An approxi-
mate expression to determine the excess inrush
current due to the dV
OUT
/dt of the output capaci-
tor C
OUT
is:
Iinrush = C
OUT
x
S
SS
x
V
OUT
0.8V
Where,
S
SS
= Softstart slew rate, 0.6V/ms for SP6123A
and 0.3V/ms for SP6123.
As the figure shows, the SS voltage controls a
variety of signals. First, provided all the exter-
nal fault conditions are removed, an internal
5
A pull-up at the COMP pin brings the SP6123
out of shutdown mode. The internal timing
circuit is then activated and controls the ramp-
up of the error amp reference voltage. The
COMP pin is pulled to 0.7V by the internal
THEORY OF OPERATION: Continued
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