Preliminary
Product Description
1
EDS-103162 Rev B
303 Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions.
Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are
subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not
authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems.
Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.
Preliminary
0
5
10
15
20
25
30
35
40
0
2
4
6
8
10
5V 40mA
3V 20mA
SPF-3143
Low Noise pHEMT GaAs FET
Product Features
DC-10 GHz Operation
0.58 dB NF
MIN
@ 2 GHz
21 dB G
MAX
@ 2 GHz
+31 dBm OIP3 (5V,40mA)
+18 dBm P1dB (5V,40mA)
Low Current, Low Cost
Apps circuits available for key bands
Applications
Analog and Digital Wireless Systems
3G, Cellular, PCS
Fixed Wireless, Pager Systems
Driver Stage for Low Power Applications
Sirenza Microdevices' SPF-3143 is a high performance
0.5
m pHEMT Gallium Arsenide FET. This 600m device is
ideally biased at 3V,20mA for lowest noise performance and
battery powered requirements. At 5V,40mA the device can
deliver OIP3 of 31dBm. It provides ideal performance as a
driver stage in many commercial and industrial LNA
applications.
Typical Gain Performance
Frequency (GHz)
Gain, Gmax (dB)
Gmax
Gain
Symbol
Device Characteristics
Test Condition
V
DS
=5V, I
DQ
=40mA, 25C
(unless otherwise noted)
Test
Frequency
Units
Min
Typ
Max
G
MAX
Maximum Available Gain
Z
S
=Z
S
*, Z
L
= Z
L
*
0.9GHz
1.9GHz
dB
23.3
19.9
NF
MIN
Minimum Noise Figure
Z
S
=
OPT
, Z
L
= Z
L
*
0.9GHz
1.9GHz
dB
0.36
0.58
S
21
Insertion Gain
Z
S
=Z
L
=50
0.9GHz
dB
20.1
NF
Noise Figure
LNA Application Circuit Board
1.9GHz
dB
0.9
Gain
Gain
LNA Application Circuit Board
1.9GHz
dB
15.1
OIP
3
Output 3rd Order Intercept Point
LNA Application Circuit Board
1.9GHz
dBm
31.0
P
1dB
Output 1dB Compression Point
LNA Application Circuit Board
1.9GHz
dBm
17.7
V
P
Pinchoff Voltage
V
DS
=2V, I
DS
=0.1mA
V
-1.4
-1.0
-0.6
I
DSS
Saturated Drain Current
V
DS
=2V, V
GS
=0V
mA
180
g
m
Transconductance
V
DS
=2V, V
GS
=-0.3V
mS
210
BV
GSO
Gate-Source Breakdown Voltage
I
GS
=300uA, drain open
V
-10
-7
BV
GDO
Gate-Drain Breakdown Voltage
I
GD
=300uA, source open
V
-12
-10
Rth
Thermal Resistance
junction to lead
C/W
200
V
DS
Operating Voltage
drain-source
V
5.5
I
DS
Operating Current
drain-source
mA
55
SPF-3143 Low Noise pHEMT GaAs FET
2
EDS-103162 Rev B
303 Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
Preliminary
Absolute Maximum Ratings
q
e
r
F
)
z
H
G
(
V
S
D
)
V
(
I
Q
D
)
A
m
(
F
N
N
I
M
]
4
[
)
B
d
(
x
a
m
G
)
B
d
(
B
d
1
P
]
5
[
)
m
B
d
(
3
P
I
O
]
6
[
)
m
B
d
(
0
9
.
0
3
0
2
5
2
.
0
5
.
1
2
5
1
9
2
5
0
4
6
3
.
0
3
.
3
2
8
1
1
3
0
9
.
1
3
0
2
0
5
.
0
3
.
8
1
5
1
9
2
5
0
4
8
5
.
0
1
.
9
1
8
1
1
3
[4]
Z
S
=
OPT
, Z
L
=Z
L
*, The input matching circuit losses have been de-emebedded.
[5]
Z
S
=Z
SOPT
, Z
L
=Z
LOPT
, where Z
SOPT
and Z
LOPT
have been tuned for max P1dB
[6]
Z
S
=Z
SOPT
, Z
L
=Z
LOPT
, where Z
SOPT
and Z
LOPT
have been tuned for max OIP3
Note: Optimum NF, P1dB, and OIP3 performance cannot be achieved simultaneously.
Peak RF Performance Under Optimum Matching Conditions
S
G
D
Z
SOPT
Z
LOPT
Biasing Details
The SPF-3143 is a depletion mode FET and requires a
negative gate voltage to achieve pinchoff. As such, power
supply sequencing circuitry is strongly recommended to
prevent damaging bias transients during turn-on. Active
bias circuitry is also recommended to maintain a constant
drain current from part-to-part.
Junction Temperature Calculation
MTTF is inversely proportional to the device junction
temperature. For junction temperature and MTTF consid-
erations the device operating conditions should also
satisfy the following expression:
P
DC
< (T
J
- T
L
) / R
TH
where:
P
DC
= I
DS
* V
DS
(W)
T
J
= Junction Temperature (C)
T
L
= Lead Temperature (pin 2) (C)
R
TH
= Thermal Resistance (C/W)
Typical Performance - Noise Parameters
q
e
r
F
)
z
H
G
(
V
S
D
)
V
(
I
S
D
)
A
m
(
F
N
N
I
M
]
7
[
)
B
d
(
T
P
O
g
a
M
g
n
A
r
N
x
a
m
G
)
B
d
(
0
9
.
0
3
0
2
5
2
.
0
0
7
.
0
1
.
2
1
4
1
.
0
5
.
1
2
5
0
4
6
3
.
0
6
6
.
0
6
.
2
1
4
1
.
0
3
.
3
2
0
9
.
1
3
0
2
0
5
.
0
6
4
.
0
4
.
6
2
3
1
.
0
3
.
8
1
5
0
4
8
5
.
0
8
3
.
0
1
.
8
2
3
1
.
0
1
.
9
1
[7]
Z
S
=
OPT
, Z
L
=Z
L
*, NF
MIN
is a noise parameter for which the input matching circuit losses have been de-emebedded. The noise
parameters were measured using a Maury Microwave Automated Tuner System. The device was mounted on a 0.010" PCB with plated-
thru holes close to pins 2 and 4.
Parameter
Symbol
Value
Unit
Drain Current
I
DS
180
mA
Forward Gate Current
I
GSF
600
uA
Reverse Gate Current
I
GSR
600
uA
Drain-to-Source Voltage
V
DS
7
V
Gate-to-Source Voltage
V
GS
<-3 OR >0
V
RF Input Power
P
IN
15
dBm
Storage Temperature Range
T
stor
-40 to + 150
C
Power Dissipation
P
DISS
325
mW
Junction Temperature
T
J
150
C
Operation of this device beyond any one of these limits may cause
permanent damage. For reliable continuous operation, the device voltage
and current must not exceed the maximum operating values specified in the
table on page 1.
SPF-3143 Low Noise pHEMT GaAs FET
3
EDS-103162 Rev B
303 Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
Preliminary
Caution: ESD sensitive
Appropriate precautions in handling, packaging and
testing devices must be observed. ESD class rating to be
determined.
L
C
5. DIE IS FACING UP FOR MOLD AND FACING DOWN
L
C
6. PACKAGE SURFACE TO BE MIRROR FINISH.
FOR TRIM/FORM. ie :REVERSE TRIM/FORM.
4. ALL SPECIFICATIONS COMPLY TO EIAJ SC70.
2. DIMENSIONS ARE INCLUSIVE OF PLATING.
3. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH
1. ALL DIMENSIONS ARE IN MILLIMETERS.
& METAL BURR.
NOTE:
D
e
HE
A2
e
E
b
b1
L
C
Q1
A
A1
Package Dimensions
F31
Use multiple plated-through vias holes located
close to the package pins to ensure a good RF
ground connection to a continuous groundplane
on the backside of the board.
Recommended PCB Layout
SOT-343
Package
Plated Thru
Holes
(0.020" DIA)
Ground
Plane
1
4
2
3
Pin Designation
Pin Description
r
e
b
m
u
N
t
r
a
P
e
z
i
S
l
e
e
R
l
e
e
R
/
s
e
c
i
v
e
D
3
4
1
3
-
F
P
S
"
7
0
0
0
3
Part Number Ordering Information
The part will be symbolized with the "F31"
designator and a dot signifying pin 1 on the top
surface of the package.
Part Symbolization
L
O
B
M
Y
S
M
O
N
E
5
2
.
1
D
5
0
.
2
E
H
0
1
.
2
A
5
0
.
1
2
A
0
9
.
0
1
A
5
0
.
0
1
Q
5
2
.
0
e
5
6
.
0
b
5
7
3
.
0
1
b
5
7
6
.
0
c
4
1
.
0
L
0
2
.
0
Pin #
Function
Description
1
Gate
RF Input / Gate Bias
2
Source
Connection to ground. Use via holes to reduce lead
inductance. Place vias as close to ground leads as possible.
3
Drain
RF Output / Drain Bias
4
NC
No Connection / Recommend grounding pin
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