--1--

E91Z07G86-TE

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Absolute Maximum Ratings (Ta=25 °C)

· Supply voltage V

· Reference voltage

, V

+ 0.5 to V

0.5 V

· Input voltage

+ 0.5 to V

0.5 V

(Analog)

· Input voltage

+ 0.5 to V

0.5 V

(Digital)

· Output voltage V

+ 0.5 to V

0.5 V

(Digital)

· Storage temperature

Tstg

55 to +150

°C

Recommended Operating Conditions

· Supply voltage AV

, AV

4.75 to 5.25

, DV

| DV

| 0 to 100

· Reference input voltage

0 and above

2.7 and below

· Analog input

1.8 Vp-p above

· Clock pulse width

Tpw

, Tpw

13 ns (min) to 1.1 µs (max)

· Operating ambient temperature

Topr

40 to +85

°C

Description

The CXD1179Q is an 8-bit CMOS A/D converter

for video with synchronizing clamp function. The

adoption of 2 step-parallel method achieves ultra-low

power consumption and a maximum conversion

speed of 35MSPS.

Features

· Resolution: 8-bit ± 1/2LSB (DL)

· Maximum sampling frequency: 35MSPS

· Low power consumption: 80 mW (at 35MSPS typ.)

(reference current excluded)

· Synchronizing clamp function

· Clamp ON/OFF function

· Reference voltage self bias circuit

· Input CMOS compatible

· 3-state TTL compatible output

· Single 5V power supply

· Low input capacitance: 8 pF

· Reference impedance: 330

(typ.)

Applications

Wide range of applications that require high-speed

A/D conversion such as TV and VCR.

Structure

Silicon gate CMOS IC

8-bit 35MSPS Video A/D Converter with Clamp Function

32 pin QFP (Plastic)

CXD1179Q

--2--

CXD1179Q

Block Diagram

Clock generator

Upper
data
latch

Lower
data
latch

Lower encoder
(4 BIT)

Upper encoder
(4 BIT)

Lower sampling
comparator (4 BIT)

Upper sampling
comparator (4 BIT)

Reference supply

DVss

CCP

VREF

CLE

VRBS

VRB

AVss

VRTS

CLP

TEST
(V

or Vss)

TEST
(V

or Vss)

TEST (OPEN)

CLK

TEST (DV

)

D7 (MSB)

D0 (LSB)

DVss

VRT

--5--

CXD1179Q

Pin No.

Symbol

Equivalent circuit

Description

VREF

CCP

CLE

Clamp reference voltage input.
Clamps so that the reference voltage
and the input signal during clamp
interval are equal.

Integrates the clamp control voltage.
The relationship between the changes
in CCP voltage and in V

voltage is

positive phase.

The clamp function is enabled when
CLE = Low.
The clamp function is set to off and
the converter functions as a normal
A/D converter when CLE = High.
The clamp pulse can be measured by
connecting CLE to DV

through a

several hundred

resistor.

Data is output when OE = Low.
Pins D0 to D7 are at high impedance
when OE = High.

CLAMP
PULSE

28, 31

Digital ground

NC pin

--6--

CXD1179Q

Digital Output

The following table shows the relationship between analog input voltage and digital output code.

PW1

PW0

N + 1

N + 2

N + 3

N + 4

N 3

N 2

N 1

N + 1

Td = 13ns

Clock 2V

Analog input

Data output 2V

: Analog signal sampling point

tr = 4.5ns

tf = 4.5ns

2.5V

PLZ

PHZ

10%

90%

PZH

1.3V

PZL

10%

90%

OE input

output 1

(

)

(

)

output 2

Input signal

voltage

Step

Digital output code

MSB LSB

:
:
:
:

127
128

255

1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

Timing Chart

--7--

CXD1179Q

Electrical Characteristics

Analog characteristics

(Fc = 35MSPS, V

= 5 V, V

= 0.5 V, V

= 2.5 V, Ta = 25 °C)

Conversion speed

Analog input band width
(1 dB)

Offset voltage

Integral non-linearity error

Differential non-linearity error

Differential gain error

Differential phase error

Aperture jitter

Sampling delay

Clamp offset voltage

Clamp pulse delay

Eoc

cpd

0.5

+55

= 4.75 to 5.25 V

Ta = 40 to +85 °C
V

= 0.5 to 2.5 V

= 1 kHz ramp

Envelope

Potential difference to V

End point

NTSC 40 IRE mod ramp
Fc = 14.3MSPS

= DC,

PWS = 3 µs

+75

+0.5

±0.3

0.5

+95

+1.3
1.0

±0.5

+20

+10

MSPS

MHz

LSB

deg

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

REF

= 0.5 V

REF

= 2.5 V

The offset voltage EOB is a potential difference between V

and a point of position where the voltage

drops equivalent to 1/2 LSB of the voltage when the output data changes from "00000000" to "00000001".

EOT is a potential difference between V

and a potential of point where the voltage rises equivalent to

1/2LSB of the voltage when the output data changes from "11111111" to "11111110".

Clamp offset voltage varies individually. When using with R, G, B 3 channels, color sliding may be

generated.

--8--

CXD1179Q

DC characteristics

(Fc = 35MSPS, V

= 5 V, V

= 0.5 V, V

= 2.5 V, Ta = 25 °C)

Supply current

Reference pin current

Analog input capacitance

Reference resistance
(V

to V

)

Self-bias

Digital input voltage

Digital input current

Digital output current

REF

RB1

RT1

RB1

RT2

OZH

OZL

4.5

230

0.52

1.96

2.13

3.5

1.1

3.7

Fc = 35MSPS
NTSC ramp wave input

= 1.5 V + 0.07 Vrms

Shorts VRB and VRBS
Shorts VRT and VRTS

VRB = AGND
Shorts VRT and VRTS

= 4.75 to 5.25 V

Ta = 40 to +85 °C

= max

OE = V

= min

OE = V

= max

6.1

330

0.56

2.10

2.33

2.5

6.5

8.7

440

0.60

2.24

2.53

0.5

µA

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

Timing

(Fc = 35MSPS, V

= 5 V, V

= 0.5 V, V

= 2.5 V, Ta = 25 °C)

Output data delay

Tri-state output
enable time

Tri-state output
disable time

Clamp pulse width

PZH

PZL

PHZ

PLZ

cpw

1.75

With TTL 1 gate and 10 pF load
V

= 4.75 to 5.25 V

Ta = 40 to +85 °C

= 1 k

, C

= 15 pF

OE = 5 V

0 V

= 4.75 to 5.25 V

Ta = 40 to +85 °C

= 1 k

, C

= 15 pF

OE = 0V

5 V

= 4.75 to 5.25 V

Ta = 40 to +85 °C

Fc = 14MSPS, C

= 10 µF

for NTSC wave

6.5

2.75

3.75

µs

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

= V

= 0 V

= V

0.5 V

= 0.4 V

= V

= 0 V

The clamp pulse width is for NTSC as an example. Adjust the rate to the clamp pulse cycle (1/15.75 kHz

for NTSC) for other processing systems to equal the values for NTSC.

--9--

CXD1179Q

Electrical Characteristics Measurement Circuit

Integral non-linearity error

Differential non-linearity error

}

measurement circuit

Offset voltage

A < B A > B

COMPARATOR

A1
A0

B1
B0

DUT

CXD1179Q

BUFFER

CONTROLLER

DVM

CLK (35MHz)

"0"

"1"

S1: ON

A < B

S2: ON

B > A

000 · · · 00

111 · · · 10

Maximum operational speed

Differential gain error

}

measurement circuit

Differential phase error

S.G.

NTSC

SIGNAL

SOURCE

S.G.

(CW)

CXD
1179Q

10bit

D/A

VECTOR

SCOPE

COUNTER

H.P.F

TTL

ECL

AMP

TTL

ECL

620

5.2V

CLK

620

5.2V

CX20202A-1

ERROR RATE

D.G
D.P.

40 IRE
MODULATION

100

SYNC

0.5V

2.5V

I
A

BURST

2.5V

0.5V

Fc 1kHz

Digital output current measurement circuit

CLK

GND

2.5V

0.5V

CLK

GND

2.5V

0.5V

Measurement
point

To output pin

Tri-state output measurement circuit

Note) C

includes capacitance of the probe and others.

--10--

CXD1179Q

S (1)

C (1)

S (2)

C (2)

S (3)

C (3)

S (4)

C (4)

MD (0)

MD (1)

MD (2)

MD (3)

RV (0)

RV (1)

RV (2)

RV (3)

S (1)

C (1)

S (3)

C (3)

H (3)

H (1)

LD (1)

C (0)

S (2)

C (2)

S (4)

H (0)

H (2)

H (4)

LD (2)

LD (0)

LD (2)

Out (2)

Out (1)

Out (0)

Out (1)

Vi (1)

Vi (2)

Vi (3)

Vi (4)

Analog input

External clock

Upper comparators block

Upper data

Lower reference voltage

Lower comparators A block

Lower data A

Lower comparators B block

Lower data B

Digital output

Timing Chart 3

Operation (See Block Diagram and Timing Chart 3)

1. The CXD1179Q is a 2-step parallel system A/D converter featuring a 4-bit upper comparators group and 2

lower comparators groups of 4-bit each. The reference voltage that is equal to the voltage between VRT

VRB/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper

data is fed through the reference supply to the lower data. VRTS and VRBS pins serve for the self

generation of VRT (Reference voltage top) and VRB (Reference voltage bottom).

--11--

CXD1179Q

2. This IC uses an offset cancel type comparator and the comparator operates synchronously with an

external clock. These modes are respectively indicated on the timing chart with S, H, C symbols. That is,

the comparator performs input sampling (auto zero) mode, input hold mode and comparison mode using

the external clock.

3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled

with the falling edge of the first clock by means of the upper comparator block and the lower comparator A

block.

The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock.

Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to

the upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the

second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock.

Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output.

Operation Notes

1. Power supply and ground

To reduce noise effects, separate the analog and digital systems close to the device. For both the digital

and analog power supply pins, use a ceramic capacitor of about 0.1 µF set as close as possible to the pin

to bypass to the respective grounds.

2. Analog input

Compared with the flash type A/D converter, the input capacitance of the analog input is rather small.

However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability.

When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be

prevented by inserting a resistance of about 100

in series between the amplifier output and A/D input.

3. Clock input

The clock line wiring should be as short as possible also, to avoid any interference with other signals,

separate it from other circuits.

4. Reference input

Voltage between V

to V

is compatible with the dynamic range of the analog input. Bypassing VRT and

VRB pins to analog ground, by means of a capacitor about 0.1 µF, the stable characteristics of the

reference voltage are obtained. By shorting VRT and VRTS, VRB and VRBS, the self-bias function that

generates V

= about 2.6 V and V

= about 0.6 V, is activated.

5. Timing

Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks

and with the following rising edge. The delay from the clock rising edge to the data output is about 13ns.

6. OE pin

By connecting OE to DV

output mode is obtained. By connecting OE to DV

high impedance is

obtained.

--12--

CXD1179Q

Application Circuit

(1) When clamp is used (self bias used)

0.1µ

OPEN

LATCH

0.01µ

CLAMP PULSE IN

CLOCK IN

ACO4

+5V (Analog)

VIDEO IN

10µ

0.1µ

10P

+5V (Analog)

0.01µ

VREF

20k

GND (Analog)

0.01µ

GND (Digital)

+5V (Digital)

The clamp pulse is latched by the sampling clock of ADC, but that is not necessary for basic clamp operation.

However, slight small beat may be generated as vertical sag according to the relationship between the

sampling frequency and the clamp pulse frequency. At such time, the latch circuit is effective in this case.

--13--

CXD1179Q

(2) Digital clamp (self bias used)

0.1µ

OPEN

0.01µ

CLOCK IN

ACO4

+5V (Analog)

VIDEO IN

10µ

0.1µ

10P

0.01µ

GND (Analog)

GND (Digital)

DAC,
PWM,
etc.

Latch,
Subtracter,
Comparator,
etc.

CLAMP
PULSE IN

+5V (Digital)

Clamp Level
setting data

(3) When clamp is not used (self bias used)

OPEN

0.01µ

CLOCK IN

ACO4

+5V (Analog)

VIDEO IN

0.1µ

10P

0.01µ

GND (Analog)

GND (Digital)

+5V (Digital)

0.1µ

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