Structure

Silicon gate CMOS IC

CXD2310AR

E95429B5X-PK

10-bit 20MSPS Video A/D Converter

Description

The CXD2310AR is a 10-bit CMOS A/D converter

for video applications. This IC is ideally suited for the

A/D conversion of video signals in TVs, VCRs,

camcorders, etc.

Features

· Resolution: 10-bit ±1.0 LSB (D.L.E.)

· Maximum sampling frequency: 20MSPS

· Low power consumption: 150mW (at 20MSPS typ.)

(Not including reference current)

· TTL compatible input

· Tri-state TTL compatible output (DV

= 3.3V)

· Low input capacitance

· Reference impedance: 280

(typ.)

Absolute Maximum Ratings (Ta = 25°C)

· Supply voltage

· Reference voltage

VRT, VRB

+ 0.5 to V

0.5

· Input voltage (analog)

+ 0.5 to V

0.5

· Input voltage (digital)

, V

+ 0.5 to V

0.5

· Output voltage (digital)

, V

+ 0.5 to V

0.5

· Storage temperature

Tstg

55 to +150

°C

Recommended Operating Conditions

· Supply voltage

, AV

5.0 ± 0.25

, DV

3.0 to 5.25

| DV

0 to 100

· Reference input voltage

VRB

More than 1.8

VRT

to AV

0.4

· Analog input

More than 1.8Vp-p

· Clock pulse width

25 (min.)

· Operating ambient temperature

Topr

20 to +75

°C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

48 pin LQFP (Plastic)

CXD2310AR

Block Diagram

DAC

Coarse

Comparate

Encode

Calibration

Unit

Fine

Comparate

Encode

Fine

Latch

Coarse

Correction

Latch

Timing Gen

D0 (LSB)

MINV

LINV

TESTMODE

CAL

SEL

RESET

VRT

VRB

CLK

27 28

Sense

Amp

Sense

Amp

Auto Calibration

Pulse Generator

S/H

Amp

Pin Configuration

CLK

MINV

LINV

TESTMODE

SEL

RESET

TIN

TSTR

CAL

VRB

VRT

9 10 11 12

36 35 34

CXD2310AR

Pin No

Symbol

Equivalent circuit

Description

1 to 5

8 to 12

D0 to D9

7, 45

6, 16, 48

27, 28, 36,

43, 44

SEL

CLK

CAL

RESET

D0 (LSB) to D9 (MSB)
output.

Test pin.
TS = High:

High impedance state

Digital V

Analog V

Calibration input pulse
select after completion of
the startup calibration.
High : Internal pulse

generation

Low : External input

Clock pin.

Calibration pulse input.

Calibration circuit reset
and startup calibration
restart.

Pin Description

CXD2310AR

Pin No.

Symbol

Equivalent circuit

Description

TIN

34, 35

VRB

Test signal input.
Normally fixed to AV

Reference top.

Reference bottom.

Test signal output.
TS = High:

High impedance state

D0 to D9 output enable.
Low : Output state
High : High impedance

state

Chip enable.
Low : Active state
High : Standby state

29, 30

VRT

TSTR

Test signal input.
Normally fixed to AV

CXD2310AR

Input signal voltage

Digital output code

MSB LSB

Step

VRT

VRB

1 1 1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 0

511
512

1023

TESTMODE

LINV

MINV

1
1
1
1
0
0
0
0

0
1
0
1
0
1
0
1

0
0
1
1
0
0
1
1

1
0
1
0

0
1
0
1

1
0
1
0

0
1
0
1

1
0
1
0

0
1
0
1

1
0
1
0

0
1
0
1

1
0
1
0

P
P

N
N

0
0
1
1

Digital Output

The following table shows the correlation between the analog input voltage and the digital output code

(TESTMODE = 1, LINV, MINV = 0)

The following table shows the output state for the combination of TESTMODE, LINV, and MINV states.

P: Forward-phase output N: Inverted output

Timing Chart 1

N + 1

N + 2

N + 3

N + 4

: Indicates point at which analog data is sampled

Clock

Analog input

Data output

N 3

N 2

N 1

1.65V

1.65V (DV

= 3.3V)

2.5V (DV

= 5.0V)

Timing Chart 2

High Impedance

PEZ

PZE

Active

1.65V

Output enable (OE)

Data output

1.65V (DV

= 3.3V)

2.5V (DV

= 5.0V)

CXD2310AR

Electrical Characteristics

(Fc = 20MSPS, AV

= 5V, DV

= 3.3V, VRB = 2.0V, VRT = 4.0V, Ta = 25°C)

Fc max

Fc min

REF

CAL

OZH

OZL

PEZ

PZE

Max. conversion rate

Min. conversion rate

Analog

Digital

Analog

Digital

Analog input band

Analog input capacitance

Reference resistance value
(VRT VRB)

Tri-state output disable time

Tri-state output enable time

Integral non-linearity error

Differential non-linearity error

Differential gain error

Differential phase error

Output data delay

Sampling delay

5.0

11.0

180

120

2.3

3.5

3.0

7.0

280

2.5

1.0

±1.3

±0.5

1.0

0.3

0.5

1.0

11.0

5.0

380

140

0.8

±2.0

±1.0

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

Supply
current

MSPS

µA

MHz

µA

deg

LSB

Standby
current

Reference pin current

Offset voltage

Analog input current

Startup calibration start
voltage

Digital input voltage

Digital input current

Digital output current

= 1.0kHz

triangular wave input

= 1.0kHz

triangular wave input

CE = High

= theoretical value-actual

measured value
EOB = actual measured value-
theoretical value

1dB

= DV

0.5V

= 0.4V

= DV

= 0V

= max

OE = AV

= min

Clock not synchronized for
active

high impedance

Clock not synchronized for high
impedance

active

NTSC 40 IRE mod
ramp, Fc = 14.3MSPS

= 4.75V to 5.25V

= 20pF

= 0V

= DV

= 4V

= 2V

OE = AV

= max

VRT VRB

CXD2310AR

Application Circuit 1. Startup calibration + internal auto calibration

Digital output

2.0V

4.0V

2.0V

4.0V

Clock input

CLK

MINV

LINV

TESTMODE

SEL

RESET

TIN

TSTR

CAL

VRB

VRT

is all 0.1µF

9 10 11 12

SNR

SFDR

SNR

SFDR

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

= 100kHz

= 500kHz

= 1MHz

= 3MHz

= 7MHz

= 10MHz

= 100kHz

= 500kHz

= 1MHz

= 3MHz

= 7MHz

= 10MHz

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

CXD2310AR

Application Circuit 2. Startup calibration + external sync calibration

Digital output

2.0V

Calibration pulse

4.0V

2.0V

4.0V

Clock input

CLK

MINV

LINV

TESTMODE

SEL

RESET

TIN

TSTR

CAL

VRB

VRT

is all 0.1µF

9 10 11 12

CXD2310AR

Application Circuit 3. Only startup calibration

(Less than supply voltage fluctuation range of AV

= ±100mV and reference voltage fluctuation range of

|VRT VRB| = 200mV)

Digital output

2.0V

4.0V

2.0V

4.0V

Clock input

CLK

MINV

LINV

TESTMODE

SEL

RESET

TIN

TSTR

CAL

VRB

VRT

is all 0.1µF

9 10 11 12

Fig. 1. Calibration Pulse Generation Circuit

(1) Startup Calibration Function

Over 600 calibration pulses are needed to complete the initial calibration process when the power is first

supplied to the IC. The startup calibration function automatically generates these pulses internally and

completes the initial calibration process.

The following five conditions must be satisfied to initiate the

startup calibration function.

a) The voltage between AV

and AV

is approximately

2.5V or more.

b) The voltage between VRT and VRB is approximately 1V

or more.

c) The RESET pin (Pin 15) must is high.

d) The CE pin (Pin 24) must is low.

e) Condition b is met after condition a.

Once all five of these conditions have been met, the calibration

pulses are generated. The pulses are generated by counting 16

main clock cycles on a 14-bit counter and closing the gate when

the carry-out occurs. Therefore, the time required for startup

calibration after the above five conditions have been met is

determined by the following formula:

Startup calibration time = main clock cycle

16,384

For example, if the main clock frequency is 14.3MHz, the time required for startup calibration is 18ms.

When RESET = High and CE = Low

VRT

VRB

[V]

2.5

[ t ]

Sence Amp 1

Sence Amp 2

CLR

CXD2310AR

1. Calibration Function

In order to achieve superior linearity, the CXD2310AR has a built-in calibration circuit. In order to eliminate the

necessity for the externally input calibration pulse required by the earlier CXD2310R, a startup calibration

function and an auto calibration pulse generation function have been newly added to the CXD2310AR. Fig. 1

shows a block diagram of the calibration pulse generation circuit.

OUT

14 bit
Counter

24 bit
Counter

CLR

SEL

CAL

D Q

CLK

VRT

VRB

RESET

Sence
Amp 1

Sence
Amp 2

CXD2310AR

(2) Auto Calibration Pulse Generation Function

After startup calibration is completed, this function periodically generates calibration pulses so that calibration

can be performed constantly without any need for input of calibration pulses from an external source. This

function counts 16 main clock cycles on a 24-bit counter and uses the carry-out as the calibration pulse. The

cycle of the calibration pulse generated in this fashion is as follows:

Internal calibration pulse generation cycle = main clock cycle

16,777,216

Therefore, if the main clock frequency is 14.3MHz, the calibration pulse cycle is approximately 19 seconds;

since calibration is performed once every seven pulses, the calibration cycle is approximately 130 seconds. In

order to use this function, the SEL pin (Pin 17) must be high.

Note that this function cannot be used if fixing the lower bits in the calibration operation as described below will

cause problems because this function is executed asynchronously without regard to the input signals.

(3) External Calibration Pulse Input Function

If the auto calibration function cannot be used, calibration can be performed in synchronization with the input

signals when a calibration pulse is input from the CAL pin (Pin 41) by setting the SEL pin (Pin 17) low.

7clock

1clock or more

CLK

CAL

D5 to D9

D0 to D4

10ns or more

N 3

N 2

N 1

N + 1 N + 2

N + 3

N + 4

N + 5

N 3

N 2

N 1

N + 5

Fig. 2. Calibration Timing Chart

Calibration starts when the falling edge of the pulse input to the CAL pin (Pin 41) is detected. Because the

lower comparator is occupied for four clock cycles at this point, the previous lower data is held for four clock

cycles after seven clock cycles since the rising edge of the clock cycle in which the falling edge of CAL was

detected. Calibration can be performed outside of video intervals by using the sync signal, etc., to input the

CAL signal. An example of this is shown below.

(1) Inputting CAL every H-sync

Input

CLK

CAL

CXD2310AR

(2) Inputting CAL every V-sync

Input

CLK

RESET

CAL

It is also possible to use only the startup calibration function by leaving the SEL pin (Pin 1/) low and fixing the

CAL pin (Pin 41) either high or low. Note that this method requires restriction of the fluctuation range of the

supply voltage and the reference voltage.

(4) Re-initiating the Startup Calibration Function

The startup calibration function can be re-initiated after the power and reference voltage are supplied by using

the CE pin (Pin 24) and the RESET pin (Pin 15). Particularly in cases where the riseup characteristics of the

power supply and the reference voltage are unstable or the order of the riseup is not kept, it is possible to

initiate startup calibration properly by connecting a CR and delaying startup until after power supply riseup.

RESET

[V]

[ t ]

RESET

VRT

VRB

Fig. 3. Initiation of the Startup Calibration Function Using the RESET pin

CXD2310AR

2. Power supply

To prevent the influence of noise, connect the power supply to a 0.1µF by-pass capacitor as near the device

as possible.

3. DV

Either a 3.3V or 5.0V digital power supply can be used. Compared to the 5.0V power supply, the 3.3V power

supply generates a decreased amount of radiation noise but offers a decreased drive capacity. These two

power supplies do not virtually differ in static and dynamic characteristics. Further, the High output level rises

up to DV

4. Reference input

The voltage to be supplied to the reference pins must be driven by a buffer having a 10mA or more drive

capacity. For supplied voltage stabilization, connect the buffer to a 0.1µF by-pass capacitor as near the pins as

possible.

5. Latch-up

Ensure that the AV

and DV

pins share the same power supply on a board to prevent latch-up which may

be caused by power ON time-lag.

6. Board

To obtain full-expected performance from this IC, be sure that the mounting board has a large ground pattern

for lower impedance. It is recommended that the IC be mounted on a board without using a socket to evaluate

its characteristics adequately.

CXD2310AR

Supply current vs. Ambient temperature

Fc = 20MHz
fin = 1kHz ramp wave
AV

= 5.0V

= 3.3V

Output data delay vs Ambient temperature

= 5.0V

= 3.3V

Fc = 1MHz
CL = 20pF

100k

10M

Input frequency vs. SNR

= 5.0V

= 3.3V

Fc = 20MHz
V

= 2Vp-p

Ta = 25°C

100k

10M

Input frequency vs. Effective bits

= 5.0V

= 3.3V

Fc = 20MHz
V

= 2Vp-p

Ta = 25°C

100k

10M

Input frequency vs. SFDR

= 5.0V

= 3.3V

Fc = 20MHz
V

= 2Vp-p

Ta = 25°C

Sampling delay vs. Ambient temperature

= 5.0V

= 3.3V

Fc = 1MHz

Maximum operating frequency vs.

Ambient temperature

fin = 1kHz ramp wave
AV

= 5.0V

= 3.3V

100k

10M

Input band

= 5.0V

= 3.3V

Fc = 20MHz
V

= 2Vp-p

Ta = 25°C

Ambient temperature [°C]

Supply current [mA]

Maximum operating frequency [MHz]

Ambient temperature [°C]

Output data delay [ns]

Sampling delay [ns]

Input frequency [Hz]

SNR [dB]

SFDR [dB]

Input frequency [Hz]

Effective bits [bit]

Output level [dB]

Example of Representative Characteristics

CXD2310AR

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

PLATING

42/COPPER ALLOY

PACKAGE STRUCTURE

48PIN LQFP (PLASTIC)

9.0 ± 0.2

7.0 ± 0.1

(0.22)

0.18 0.03

+ 0.08

0.5 ± 0.08

(8.0)

0.5 ±

0.2

0.127 0.02

+ 0.05

0.1 ± 0.1

0.5 ±

0.2

1.5 0.1

+ 0.2

0° to 10°

DETAIL A

0.2g

LQFP-48P-L01

LQFP048-P-0707

0.1

SOLDER/PALLADIUM

NOTE: Dimension "

" does not include mold protrusion.

Package Outline

Unit : mm

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXD2310

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXD2310