Timing Generator for Frame Readout CCD Image Sensor
Description
The CXD2470R is a timing generator IC which
generates the timing pulses for performing frame
readout using the ICX224,ICX284,ICX202 and ICX232
CCD image sensor.
Features
Base oscillation frequency 24.00 to 36.00MHz (max.)
High-speed/low-speed shutter function
Supports quadruple-speed readout drive
Horizontal driver for CCD image sensor
Vertical driver for CCD image sensor
Applications
Digital still cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX224 (Type 1/2, 2020K pixels)
ICX284 (Type 1/2.7, 2020K pixels)
ICX202 (Type 1/3, 1250K pixels)
ICX232 (Type 1/3.6, 1250K pixels)
Pin Configuration
Absolute Maximum Ratings
Supply voltage
V
DD
V
SS
0.3 to +7.0
V
V
L
10.0 to V
SS
V
V
H
V
L
0.3 to +26.0
V
Input voltage
V
I
V
SS
0.3 to V
DD
+ 0.3
V
Output voltage
V
O1
V
SS
0.3 to V
DD
+ 0.3
V
V
O2
V
L
0.3 to V
SS
+ 0.3
V
V
O3
V
L
0.3 to V
H
+ 0.3
V
Operating temperature
Topr
20 to +75
C
Storage temperature
Tstg
55 to +150
C
Recommended Operating Conditions
Supply voltage
V
DD
b
3.0 to 5.5
V
V
DD
a, V
DD
c, V
DD
d
3.0 to 3.6
V
V
M
0.0
V
V
H
14.5 to 15.5
V
V
L
7.0 to 8.0
V
Operating temperature
Topr
20 to +75
C
1
E98Y31C9Z-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXD2470R
48 pin LQFP (Plastic)
Groups of pins enclosed in the figure indicate
sections for which power supply separation is
possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
H2
V
DD
3
V
DD
4
XSHP
XSHD
XRS
PBLK
CLPDM
V
SS
4
OBCLP
ADCLK
V
SS
5
CKO
CKI
OSCO
OSCI
V
DD
5
MCKO
SSI
SCK
SEN
VDI
HDI
V
SS
6
H1
V
SS
3
V
SS
2
RG
V
DD
2
EBCKSM
V
DD
1
WEN
ID
DSGA
T
RST
V
SS
1
TEST2
SUB
V3B
VL
V3A
V1B
VH
V1A
V4
V2
VM
TEST1
2
CXD2470R
Block Diagram
3
2
37 48
35
34
39
44
43
41
5
4
24
23
22
20
19
21
18
17
16
15
10
9
8
11
13
12
14
28
27
26
25
30
7
29
1
V1B
V2
V3A
V1A
WEN
ID
V
SS
5
ADCLK
OBCLP
CLPDM
PBLK
V
S
S
4
X
R
S
X
S
H
D
X
S
H
P
V
D
D
4
V
S
S
2
R
G
V
D
D
2
V
S
S
3
H
2
H
1
V
D
D
3
V
D
I
H
D
I
T
E
S
T
2
T
E
S
T
1
R
S
T
D
S
G
A
T
V
SS
1
36
V
SS
6
V
DD
5
V
DD
1
MCKO
CKO
CKI
OSCO
OSCI
Pulse Generator
45
38
42
47
40
46
VL
VM
VH
SUB
V4
V3B
31
32
33
SEN
SCK
SSI
Register
V Driver
6
EBCKSM
1/2
3
CXD2470R
Pin Description
GND
Internal system reset input.
High: Normal operation, Low: Reset control
Normally apply reset during power-on.
Schmitt trigger input/No protective diode on power supply side
Control input used to stop pulse generation.
High: Normal operation, Low: Stop control
Schmitt trigger input/No protective diode on power supply side
Vertical direction line identification pulse output.
Memory write timing pulse output.
CHKSUM enable.
High: Sum check invalid, Low: Sum check valid
With pull-down resistor
3.3V power supply. (Power supply for common logic block)
3.3V power supply. (Power supply for RG)
CCD reset gate pulse output.
GND
GND
CCD horizontal register clock output.
CCD horizontal register clock output.
3.3 to 5.0V power supply. (Power supply for H1/H2)
3.3V power supply. (Power supply for CDS block)
CCD precharge level sample-and-hold pulse output.
CCD data level sample-and-hold pulse output.
Sample-and-hold pulse output for analog/digital conversion phase alignment.
Pulse output for horizontal and vertical blanking period pulse cleaning.
CCD dummy signal clamp pulse output.
GND
CCD optical black signal clamp pulse output.
Clock output for analog/digital conversion IC.
Logical phase adjustment possible using the serial interface data.
GND
Inverter output.
Inverter input.
Inverter output for oscillation.
When not used, leave open or connect a capacitor.
Inverter input for oscillation.
When not used, fix low.
3.3V power supply. (Power supply for common logic block)
System clock output for signal processing IC.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
1
RST
DSGAT
ID
WEN
EBCKSM
V
DD
1
V
DD
2
RG
V
SS
2
V
SS
3
H1
H2
V
DD
3
V
DD
4
XSHP
XSHD
XRS
PBLK
CLPDM
V
SS
4
OBCLP
ADCLK
V
SS
5
CKO
CKI
OSCO
OSCI
V
DD
5
MCKO
--
I
I
O
O
I
--
--
O
--
--
O
O
--
--
O
O
O
O
O
--
O
O
--
O
I
O
I
--
O
Pin
No.
Symbol
I/O
Description
4
CXD2470R
Serial interface data input for internal mode settings.
Schmitt trigger input/No protective diode on power supply side
Serial interface clock input for internal mode settings.
Schmitt trigger input/No protective diode on power supply side
Serial interface strobe input for internal mode settings.
Schmitt trigger input/No protective diode on power supply side
Vertical sync signal input.
Schmitt trigger input
Horizontal sync signal input.
Schmitt trigger input
GND
IC test pin 1; normally fixed to GND.
With pull-down resistor
GND (GND for vertical driver)
CCD vertical register clock output.
CCD vertical register clock output.
CCD vertical register clock output.
15.0V power supply. (Power supply for vertical driver)
CCD vertical register clock output.
CCD vertical register clock output.
7.5V power supply. (Power supply for vertical driver)
CCD vertical register clock output.
CCD electronic shutter pulse output.
IC test pin 2; normally fixed to GND.
With pull-down resistor
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SSI
SCK
SEN
VDI
HDI
V
SS
6
TEST1
VM
V2
V4
V1A
VH
V1B
V3A
VL
V3B
SUB
TEST2
I
I
I
I
I
--
I
--
O
O
O
--
O
O
--
O
O
I
Pin
No.
Symbol
I/O
Description
5
CXD2470R
Electrical Characteristics
DC Characteristics
(Within the recommended operating conditions)
V
DD2
V
DD3
V
DD4
V
DD1
, V
DD5
RST, DSGAT,
SSI, SCK,
SEN,
EBCKSM
TEST1,
TEST2
VDI, HDI
H1, H2
RG
XSHP, XSHD,
XRS, PBLK,
OBCLP,
CLPDM,
ADCLK
CKO, MCKO
V1A, V1B,
V3A, V3B,
V2, V4
SUB
V
DD
a
V
DD
b
V
DD
c
V
DD
d
V
t+
V
t
V
IH1
V
IL1
V
IH2
V
IL2
V
OH1
V
OL1
V
OH2
V
OL2
V
OH3
V
OL3
V
OH4
V
OL4
I
OL
I
OM1
I
OM2
I
OH
I
OSL
I
OSH
3.0
3.0
3.0
3.0
0.8V
DD
d
0.7V
DD
d
0.7V
DD
d
V
DD
b 0.8
V
DD
b 0.8
V
DD
c 0.8
V
DD
d 0.8
10.0
5.0
5.4
3.3
3.3
3.3
3.3
3.6
5.5
3.6
3.6
0.2V
DD
d
0.3V
DD
d
0.3V
DD
d
0.4
0.4
0.4
0.4
5.0
7.2
4.0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
Feed current where I
OH
= 22.0mA
Pull-in current where I
OL
= 14.4mA
Feed current where I
OH
= 3.3mA
Pull-in current where I
OL
= 2.4mA
Feed current where I
OH
= 3.3mA
Pull-in current where I
OL
= 2.4mA
Feed current where I
OH
= 10.4mA
Pull-in current where I
OL
= 7.2mA
V1A/B, V2, V3A/B, V4 = 8.25V
V1A/B, V2, V3A/B, V4 = 0.25V
V1A/B, V3A/B = 0.25V
V1A/B, V3A/B = 14.75V
SUB = 8.25V
SUB = 14.75V
Supply voltage 1
Supply voltage 2
Supply voltage 3
Supply voltage 4
Input voltage 1
1
Input voltage 2
2
Input voltage 3
Output voltage 1
Output voltage 2
Output voltage 3
Output voltage 4
Output current 1
Output current 2
Item
Pins
Symbol
Conditions
Min.
Typ.
Max.
Unit
1
These input pins are Schmitt trigger inputs and do not have protective diodes on the internal power supply
side.
2
These input pins have internal pull-down resistors.
Note) The above table indicates the condition for 3.3V drive.
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