Description
The CXD3003R is a digital signal processor LSI for
CD players. This LSI incorporates a digital servo,
digital filter and 1-bit DAC.
Features
All digital signal processing during playback is
performed with a single chip
Highly integrated mounting possible due to a built-
in RAM
Digital Signal Processor (DSP) Block
Playback mode supporting CAV (Constant Angular
Velocity)
Frame jitter free
0.5
to 24
continuous playback possible with a
low external clock
Allows relative rotational velocity readout
Wide capture range playback mode
Spindle rotational velocity following method
Supports 1
to 24
playback by switching the built-
in VCO
The bit clock, which strobes the EFM signal, is
generated by the digital PLL
EFM data demodulation
Enhanced EFM frame sync signal protection
Refined super strategy-based powerful error
correction
C1: double correction, C2: quadruple correction
Supported during 24
playback
Noise reduction during track jumps
Auto zero-cross mute
Subcode demodulation and Sub Q data error
detection
Digital spindle servo (built-in oversampling filter)
16-bit traverse counter
Asymmetry compensation circuit
CPU interface on serial bus
Error correction monitor signal, etc. output from a
new CPU interface
Servo auto sequencer
Fine search performs track jumps with high
accuracy
Digital audio interface outputs
Digital level meter, peak meter
Bilingual compatible
VCO control mode
Digital Servo (DSSP) Block
Microcomputer software-based flexible servo
control
Offset cancel function for servo error signal
Auto gain control function for servo loop
E:F balance, focus bias adjustment function
Surf jump function supporting micro two-axis
Digital Filter and DAC Blocks
Digital de-emphasis
Digital attenuation
4Fs oversampling filter
Adoption of a secondary
noise shaper
Supports double-speed playback
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
Supply voltage
V
DD
0.3 to +4.6
V
Input voltage
V
I
0.3 to +4.6
V
(V
SS
0.3V to V
DD
+ 0.3V)
Output voltage
V
O
0.3 to +4.6
V
Storage temperature Tstg
40 to +125
C
Supply voltage difference
V
SS
AV
SS
0.3 to +0.3
V
V
DD
AV
DD
0.3 to +0.3
V
Recommended Operating Conditions
Supply voltage
V
DD
3.0 to 4.0
V
Operating temperature
Topr
20 to +75
C
The V
DD
(min.) for the CXD3003R varies
according to the playback speed and built-in VCO
selection. The V
DD
(min.) for the CXD3003R under
various conditions are as shown on the following
page.
1
CXD3003R
E97306A88
CD Digital Signal Processor with Built-in Digital Servo and DAC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
144 pin LQFP (Plastic)
For the availability of this product, please contact the sales office.
5
CXD3003R
Pin Description
Pin
No.
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
39
40
I
I
I
O
O
I
O
I
O
I
I
I
I
O
I
I
O
O
I
O
I
O
I
O
O
O
O
O
O
1, Z, 0
1, Z, 0
Analog
1, Z, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
Sled error signal input.
Focus error signal input.
Center voltage input.
Wide-band EFM PLL VCO2 charge pump output.
Wide-band EFM PLL VCO2 charge pump output 2. Turned on and off by $E
command FCSW.
Wide-band EFM PLL VCO2 control voltage input.
Master PLL filter output (slave = digital PLL).
Master PLL filter input.
Master PLL charge pump output.
Multiplier VCO control voltage input.
Analog GND.
EFM signal input.
Asymmetry circuit constant current input.
Asymmetry comparator voltage input.
EFM full-swing output (low = V
SS
, high = V
DD
).
Analog power supply.
Digital power supply.
Digital GND.
Asymmetry circuit on/off (low = off, high = on).
Audio data output mode switching input (low: serial, high: parallel).
D/A interface for 48-bit slot. Word clock f = 2Fs.
D/A interface for 48-bit slot. LR clock f = Fs.
LR clock input to DAC (48-bit slot).
DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two's
complement, MSB first) when PSSL = 0.
Audio data input to DAC (48-bit slot).
DA15 output when PSSL = 1, 48-bit slot bit clock output when PSSL = 0.
Bit clock input to DAC (48-bit slot).
DA14 output when PSSL = 1, 64-bit slot serial data output (two's
complement, LSB first) when PSSL = 0.
DA13 output when PSSL = 1, 64-bit slot bit clock output when PSSL = 0.
DA12 output when PSSL = 1, 64-bit slot LR clock output when PSSL = 0.
DA11 output when PSSL = 1, GTOP output when PSSL = 0.
DA10 output when PSSL = 1, XUGF output when PSSL = 0.
DA09 output when PSSL = 1, XPLCK output when PSSL = 0.
SE
FE
VC
VPCO1
VPCO2
VCTL
FILO
FILI
PCO
CLTV
AV
SS
1
RFAC
BIAS
ASYI
ASYO
AV
DD
1
DV
DD
1
DV
SS
1
ASYE
PSSL
WDCK
LRCK
LRCKI
DA16
PCMDI
DA15
BCKI
DA14
DA13
DA12
DA11
DA10
DA09
Symbol
I/O
Description
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