1
ICX039DLB
E96127B99
Diagonal 8mm (Type 1/2) CCD Image Sensor for CCIR Black-and-White Video Cameras
Description
The ICX039DLB is an interline CCD solid-state
image sensor suitable for CCIR black-and-white video
cameras with a diagonal 8mm (Type 1/2) system.
Smear, sensitivity, D-range, S/N and other
characteristics have been greatly improved compared
with the ICX039BLB. High sensitivity and low dark
current are achieved through the adoption of HAD
(Hole-Accumulation Diode) sensors.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time. Also, this outline is miniaturized by using
original package.
This chip is compatible with and can replace the
ICX039BLB.
Features
Low smear (20dB compared with the ICX039BLB)
High sensitivity (+3.0dB compared with the ICX039BLB)
High D range (+2.5dB compared with the ICX039BLB)
High S/N
High resolution and low dark current
Excellent antiblooming characteristics
Continuous variable-speed shutter
Substrate bias:
Adjustment free (external adjustment also possible with 6 to 14V)
Reset gate pulse:
5Vp-p adjustment free (drive also possible with 0 to 9V)
Horizontal register:
5V drive
Maximum package dimensions:
13.2mm
Device Structure
Interline CCD image sensor
Image size:
Diagonal 8mm (Type 1/2)
Number of effective pixels: 752 (H)
582 (V) approx. 440K pixels
Total number of pixels:
795 (H)
596 (V) approx. 470K pixels
Chip size:
7.95mm (H)
6.45mm (V)
Unit cell size:
8.6m (H)
8.3m (V)
Optical black:
Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction : Front 12 pixels, rear 2 pixels
Number of dummy bits:
Horizontal 22
Vertical 1 (even fields only)
Substrate material:
Silicon
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
16 pin DIP (Ceramic)
Pin 1
V
3
40
2
12
Pin 9
H
Optical black position
(Top View)
2
ICX039DLB
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
2
3
4
5
6
7
8
V
4
V
3
V
2
SUB
V
1
V
L
V
DD
V
OUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Substrate clock
Vertical register transfer clock
Protective transistor bias
Output circuit supply voltage
Signal output
9
10
11
12
13
14
15
16
V
GG
V
SS
GND
RD
RG
V
DSUB
H
1
H
2
Output circuit gate bias
Output circuit source
GND
Reset drain bias
Reset gate clock
Substrate bias circuit supply voltage
Horizontal register transfer clock
Horizontal register transfer clock
1
2
3
4
5
6
7
8
Note)
Note) : Photo sensor
Horizontal Register
V
e
r
t
i
c
a
l
R
e
g
i
s
t
e
r
V
L
V
1
S
U
B
V
2
V
3
V
4
V
D
D
V
O
U
T
V
G
G
V
D
S
U
B
V
S
S
G
N
D
R
D
R
G
H
1
H
2
11
12
13
14
15
16
9
10
Block Diagram and Pin Configuration
(Top View)
Pin Description
3
ICX039DLB
Item
0.3 to +50
0.3 to +18
55 to +10
15 to +20
to +10
to +15
to +17
17 to +17
10 to +15
55 to +10
65 to +0.3
0.3 to +30
30 to +80
10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
C
C
1
Ratings
Unit
Remarks
Absolute Maximum Ratings
1 +27V (Max.) when clock width < 10s, clock duty factor < 0.1%.
Substrate clock
SUB
GND
V
DD
, V
RD
, V
DSUB
, V
OUT
, V
SS
GND
Supply voltage
V
DD
, V
RD
, V
DSUB
, V
OUT
, V
SS
SUB
V
1
, V
2
, V
3
, V
4
GND
Clock input voltage
V
1
, V
2
, V
3
, V
4
SUB
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
H
1
, H
2
V
4
RG
, V
GG
GND
RG
, V
GG
SUB
V
L
SUB
Pins other than GND and
SUB
V
L
Storage temperature
Operating temperature
4
ICX039DLB
Item
V
DD
V
RD
V
GG
V
SS
V
L
V
DSUB
V
SUB
V
SUB
14.55
14.55
1.75
6.0
3
15.0
15.0
2.0
3
4
15.45
15.45
2.25
14.0
+3
V
V
V
V
%
V
RD
= V
DD
5
5
Symbol
Min.
Typ.
Max.
Unit
Remarks
Bias Conditions 2 [when used in substrate bias external adjustment mode]
Output circuit supply voltage
Reset drain voltage
Output circuit gate voltage
Output circuit source
Protective transistor bias
Substrate bias circuit supply voltage
Substrate voltage adjustment range
Substrate voltage adjustment precision
3
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same power supply as the V
L
power supply for the V driver should be used. (When CXD1267AN is used.)
4
Connect to GND or leave open.
5
The setting value of the substrate voltage (V
SUB
) is indicated on the back of the image sensor by a special
code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated
voltage. The adjustment precision is 3%. However, this setting value has not significance when used in
substrate bias internal generation mode.
V
SUB
code -- one character indication
Code and optimal setting correspond to each other as follows.
DC Characteristics
Item
Output circuit supply current
I
DD
5.0
10.0
mA
Symbol
Min.
Typ.
Max.
Unit
Remarks
V
SUB
code
Optimal setting 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0
E
f
G
h
J
K
L
m
N
P
Q
R
S
T
U
V
W
<Example> "L"
V
SUB
= 9.0V
Item
V
DD
V
RD
V
GG
V
SS
V
L
V
DSUB
SUB
14.55
14.55
1.75
14.55
15.0
15.0
2.0
1
15.0
2
15.45
15.45
2.25
15.45
V
V
V
V
V
RD
= V
DD
Symbol
Min.
Typ.
Max.
Unit
Remarks
Bias Conditions 1 [when used in substrate bias internal generation mode]
Output circuit supply voltage
Reset drain voltage
Output circuit gate voltage
Output circuit source
Protective transistor bias
Substrate bias circuit supply voltage
Substrate clock
Grounded with 390
resistor
1
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same power supply as the V
L
power supply for the V driver should be used. (When CXD1267AN is used.)
2
Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.
Grounded with 390
resistor
5
ICX039DLB
Item
Readout clock voltage
V
VT
V
VH1
, V
VH2
V
VH3
, V
VH4
V
VL1
, V
VL2
,
V
VL3
, V
VL4
V
V
I V
VH1
V
VH2
I
V
VH3
V
VH
V
VH4
V
VH
V
VHH
V
VHL
V
VLH
V
VLL
V
H
V
HL
V
RGL
V
RG
V
RGLH
V
RGLL
V
SUB
14.55
0.05
0.2
9.6
8.3
0.25
0.25
4.75
0.05
4.5
23.0
15.0
0
0
9.0
9.0
5.0
0
1
5.0
24.0
15.45
0.05
0.05
8.5
9.65
0.1
0.1
0.1
0.5
0.5
0.5
0.5
5.25
0.05
5.5
0.8
25.0
V
V
V
V
Vp-p
V
V
V
V
V
V
V
Vp-p
V
V
Vp-p
V
Vp-p
1
2
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
V
= V
VH
n V
VL
n (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Low-level coupling
Horizontal transfer
clock voltage
Reset gate clock
voltage
1
Substrate clock voltage
Vertical transfer clock
voltage
Symbol
Min.
Typ. Max. Unit
Waveform
diagram
Remarks
Item
Symbol
Min.
Typ. Max. Unit
Waveform
diagram
Remarks
1
Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven
with the following specifications.
Reset gate clock
voltage
V
RGL
V
RG
0.2
8.5
0
9.0
0.2
9.5
V
Vp-p
4
4
Clock Voltage Conditions
6
ICX039DLB
Clock Equivalent Circuit Constant
Item
Capacitance between vertical transfer clock
and GND
C
V1
, C
V3
C
V2
, C
V4
C
V12
, C
V34
C
V23
, C
V41
C
H1
C
H2
C
HH
C
RG
C
SUB
R
1
, R
2
, R
3
, R
4
R
GND
1800
2200
450
270
64
62
47
8
400
68
15
pF
pF
pF
pF
pF
pF
pF
pF
pF
Capacitance between vertical transfer clocks
Capacitance between horizontal transfer clock
and GND
Capacitance between horizontal transfer clocks
Capacitance between reset gate clock and GND
Capacitance between substrate clock and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Symbol
Min.
Typ.
Max.
Unit Remarks
H
2
H
1
C
H1
C
H2
C
HH
V
1
C
V12
V
2
V
4
V
3
C
V34
C
V23
C
V41
C
V1
C
V2
C
V4
C
V3
R
GND
R
4
R
1
R
3
R
2
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
7
ICX039DLB
Drive Clock Waveform Conditions
(1) Readout clock waveform
(2) Vertical transfer clock waveform
II
II
100%
90%
10%
0%
V
VT
tr
twh
tf
M
0V
M
2
V
1
V
3
V
2
V
4
V
VHH
V
VH
V
VHL
V
VHH
V
VHL
V
VH1
V
VL1
V
VLH
V
VLL
V
VL
V
VHH
V
VH3
V
VHL
V
VH
V
VHH
V
VHL
V
VL3
V
VL
V
VLL
V
VLH
V
VHH
V
VHH
V
VH
V
VHL
V
VHL
V
VH2
V
VLH
V
VL2
V
VLL
V
VL
V
VHH
V
VHH
V
VHL
V
VH4
V
VHL
V
VH
V
VL
V
VLH
V
VLL
V
VL4
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
V
= V
VH
n V
VL
n (n = 1 to 4)
8
ICX039DLB
(3) Horizontal transfer clock waveform
tr
twh
tf
90%
10%
twl
V
H
V
HL
(4) Reset gate clock waveform
Point A
twl
V
RG
V
RGH
V
RGL
+ 0.5V
V
RGL
+2.5V
V
RGLH
RG waveform
V
RGLL
H
1
waveform
twh
tr
tf
V
RGLH
is the maximum value and V
RGLL
is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, V
RGL
is the average value of V
RGLH
and
V
RGLL
.
V
RGL
= (V
RGLH
+ V
RGLL
)/2
Assuming V
RGH
is the minimum value during the interval twh, then:
V
RG
= V
RGH
V
RGL
9
ICX039DLB
(5) Substrate clock waveform
90%
100%
10%
0%
V
SUB
tr
twh
tf
M
M
2
V
SUB
Clock Switching Characteristics
Item
Readout clock
Vertical transfer
clock
During
imaging
During parallel-
serial
conversion
Reset gate clock
Substrate clock
V
T
V
1
, V
2
,
V
3
, V
4
H
H
1
H
2
RG
SUB
2.3
11
1.5
2.5
20
5.38
13
1.8
20
5.38
51
0.5
15
0.01
0.01
3
19
0.5
0.5
15
15
0.01
0.01
3
250
19
0.5
s
ns
ns
s
ns
s
During
readout
1
2
During drain
charge
Symbol
twh
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
twl
tr
tf
Unit
Remarks
1 When vertical transfer clock driver CXD1267AN is used.
2 tf
tr 2ns.
Item
Horizontal transfer clock
H
1
, H
2
16
20
ns
3
Symbol
two
Min.
Typ.
Max.
Unit
Remarks
3 The overlap period for twh and twl of horizontal transfer clocks H
1
and H
2
is two.
H
o
r
i
z
o
n
t
a
l
t
r
a
n
s
f
e
r
c
l
o
c
k
10
ICX039DLB
Image Sensor Characteristics
(Ta = 25C)
Item
Sensitivity
Saturation signal
Smear
Video signal shading
Dark signal
Dark signal shading
Flicker
Lag
S
Vsat
Sm
SH
Vdt
Vdt
F
Lag
500
720
600
0.00032 0.00056
20
25
2
1
2
0.5
mV
mV
%
%
%
mV
mV
%
%
1
2
3
4
4
5
6
7
8
Ta = 60C
Zone 0 and
I
Zone 0 to
II
'
Ta = 60C
Ta = 60C
Symbol
Min.
Typ.
Max.
Unit
Measurement method
Remarks
Zone Definition of Video Signal Shading
6
8
582 (V)
12
12
752 (H)
V
10
H
8
H
8
V
10
Effective pixel region
Zone 0,
I
Zone
II
,
II
'
Ignored region
11
ICX039DLB
Image Sensor Characteristics Measurement Method
Measurement conditions
1) In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions. (When used with substrate bias external adjustment, set the substrate voltage to the
value indicated on the device.)
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black (OB) level is used as the reference for the signal output, and the value measured at point [
A] in the
drive circuit example is used.
Definition of standard imaging conditions
1) Standard imaging condition
I
:
Use a pattern box (luminance: 706cd/m
2
, color temperature of 3200K halogen source) as a subject.
(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut
filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the
standard sensitivity testing luminous intensity.
2) Standard imaging condition
II
:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. Sensitivity
Set to standard imaging condition
I
. After selecting the electronic shutter mode with a shutter speed of
1/250 s, measure the signal output (Vs) at the center of the screen and substitute the value into the
following formula.
2. Saturation signal
Set to standard imaging condition
II
. After adjusting the luminous intensity to 10 times the intensity with the
average value of the signal output, 200mV, measure the minimum value of the signal output.
3. Smear
Set to standard imaging condition
II
. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to
500 times the intensity with the average value of the signal output, 200mV. When the readout clock is
stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure
the maximum value (VSm [mV]) of the signal output and substitute the value into the following formula.
4. Video signal shading
Set to standard imaging condition
II
. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so
that the average value of the signal output is 200mV. Then measure the maximum (Vmax [mV]) and
minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula.
SH = (Vmax Vmin)/200
100 [%]
Sm =
100 [%] (1/10V method conversion value)
200
VSm
500
1
10
1
S = Vs
[mV]
50
250
12
ICX039DLB
5. Dark signal
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
6. Dark signal shading
After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark
signal output and substitute the values into the following formula.
Vdt = Vdmax Vdmin [mV]
7. Flicker
Set to standard imaging condition
II
. Adjust the luminous intensity so that the average value of the signal
output is 200mV, and then measure the difference in the signal level between fields (
Vf [mV]). Then
substitute the value into the following formula.
F = (
Vf/200)
100 [%]
8. Lag
Adjust the signal output value generated by strobe light to 200mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following
formula.
Lag = (Vlag/200)
100 [%]
Vlag (lag)
Signal output 200mV
Light
FLD
V1
Strobe light
timing
Output
13
ICX039DLB
1
5
V
X
S
U
B
X
V
2
X
V
1
X
S
G
1
X
V
3
X
S
G
2
X
V
4
H
2
H
1
R
G
0
.
0
1
9
V
3
.
3
/
1
6
V
1
M
1
1
0
0
k
1
/
3
5
V
2
2
/
1
6
V
2
2
/
2
0
V
C
X
D
1
2
6
7
A
N
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
2
3
4
5
6
7
8
9
1
0
1
2
3
4
5
6
7
8
1
6
1
5
1
4
1
3
1
2
1
1
3
9
0
4
7
/
6
.
3
V
3
.
3
/
2
0
V
0
.
0
1
0
.
0
1
1
8
0
k
1
/
6
.
3
V
2
7
k
3
.
9
k
C
C
D
O
U
T
[
A
]
1
0
0
H
2
H
1
RG
RD
GN
D
Vs
s
V
DS
UB
V
GG
V
4
V
3
V
2
SU
B
V
1
V
L
V
DD
V
OU
T
I
C
X
0
3
9
D
L
B
1
0
9
Drive Circuit 1 (substrate bias internal generation mode)
14
ICX039DLB
1
5
V
X
S
U
B
X
V
2
X
V
1
X
S
G
1
X
V
3
X
S
G
2
X
V
4
H
2
H
1
R
G
0
.
0
1
9
V
3
.
3
/
1
6
V
1
M
1
5
k
4
7
k
1
5
k
0
.
1
3
9
k
0
.
1
2
7
0
k
2
7
k
5
6
k
0
.
1
1
0
0
k
1
/
3
5
V
1
/
3
5
V
1
/
3
5
V
2
2
/
1
6
V
2
2
/
2
0
V
C
X
D
1
2
6
7
A
N
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
2
4
5
6
7
8
9
1
0
1
2
3
4
5
6
7
8
9
1
0
1
6
1
5
1
4
1
3
1
2
1
1
3
9
0
4
7
/
6
.
3
V
3
.
3
/
2
0
V
0
.
0
1
0
.
0
1
1
8
0
k
1
/
6
.
3
V
2
7
k
3
.
9
k
C
C
D
O
U
T
[
A
]
1
0
0
H
2
H
1
RG
RD
GN
D
Vs
s
V
DS
UB
V
GG
V
4
V
3
V
2
SU
B
V
1
V
L
V
DD
V
OU
T
3
I
C
X
0
3
9
D
L
B
Drive Circuit 2 (substrate bias external adjustment mode)
15
ICX039DLB
Spectral Sensitivity Characteristics
(Includes lens characteristics, excludes light source characteristics)
Wave Length [nm]
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
R
e
l
a
t
i
v
e
R
e
s
p
o
n
s
e
400
800
500
900
600
1000
700
Sensor Readout Clock Timing Chart
unit : s
Odd Field
Even Field
V1
V2
V3
V4
V1
V2
V3
V4
2.5
2.6 2.5 2.5
1.5
33.6
0.2
16
ICX039DLB
Drive Timing Chart (Vertical Sync)
F
L
D
V
D
B
L
K
H
D
V
1
V
2
V
3
V
4
C
C
D
O
U
T
62
0
62
5
1
2
3
4
5
15
20
25
31
0
32
0
33
5
33
0
34
0
5
8
1
5
8
2
1
3
5
2
4
6
1
3
5
2
4
6
5
8
2
5
8
1
2
1
4
3
6
5
10
31
5
32
5
2
1
4
3
6
5
17
ICX039DLB
Drive Timing Chart (Horizontal Sync)
74
5
75
0
1
3
5
10
20
30
40
1
2
3
5
10
20
22
1
2
3
1
2
3
10
20
H
D
B
L
K
H
1
H
2
R
G
V
1
V
2
V
3
V
4
S
U
B
75
2
18
ICX039DLB
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive
shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensors.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded
30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool
sufficiently.
c) To dismount an image sensor, do not use solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Operate in clean environments (around class 1000 is appropriate).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition
exceeding the normal using condition, consult our company.
5) Exposure to high temperature or high humidity will affect the characteristics. Accordingly, avoid storage or
usage in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to too much mechanical
shocks.
19
ICX039DLB
Package Outline
Unit: mm
P
A
C
K
A
G
E
S
T
R
U
C
T
U
R
E
1
6
p
i
n
D
I
P
(
3
0
0
m
i
l
)
1
s
t
.
p
i
n
I
n
d
e
x
H
V
6
.
1
7
5
1
2
.
0
0
.
1
5
1
2
.
3
5
0
.
3
13
.2
0
.3
1
.
8
4
1.5
1
.
5
0
.
7
1
.
5
3
.
2
9
0
.
3
2
.
5
4
7.6
2
0.2
5
4
.
0
4.0
4.0
0
.2
1.0
0
.
3
1
.
2
7
0
.
6
1.8
4
1
8
9
1
6
6.1
75
12
.0
0
.1
5
12
.3
5
0
.3
8
1
1
6
9
1
.
"
A
"
i
s
t
h
e
c
e
n
t
e
r
o
f
t
h
e
e
f
f
e
c
t
i
v
e
i
m
a
g
e
a
r
e
a
.
2
.
T
h
e
p
o
i
n
t
"
B
"
o
f
t
h
e
p
a
c
k
a
g
e
i
s
t
h
e
h
o
r
i
z
o
n
t
a
l
r
e
f
e
r
e
n
c
e
.
T
h
e
p
o
i
n
t
"
B
'
"
o
f
t
h
e
p
a
c
k
a
g
e
i
s
t
h
e
v
e
r
t
i
c
a
l
r
e
f
e
r
e
n
c
e
.
3
.
T
h
e
b
o
t
t
o
m
"
C
"
o
f
t
h
e
p
a
c
k
a
g
e
i
s
t
h
e
h
e
i
g
h
t
r
e
f
e
r
e
n
c
e
.
4
.
T
h
e
c
e
n
t
e
r
o
f
t
h
e
e
f
f
e
c
t
i
v
e
i
m
a
g
e
a
r
e
a
r
e
l
a
t
i
v
e
t
o
t
h
e
c
e
n
t
e
r
o
f
t
h
e
p
a
c
k
a
g
e
(
)
i
s
(
H
,
V
)
=
(
0
,
0
)
0
.
1
5
m
m
.
5
.
T
h
e
r
o
t
a
t
i
o
n
a
n
g
l
e
o
f
t
h
e
e
f
f
e
c
t
i
v
e
i
m
a
g
e
a
r
e
a
r
e
l
a
t
i
v
e
t
o
H
a
n
d
V
i
s
1
.
6
.
T
h
e
h
e
i
g
h
t
f
r
o
m
t
h
e
b
o
t
t
o
m
"
C
"
t
o
t
h
e
e
f
f
e
c
t
i
v
e
i
m
a
g
e
a
r
e
a
i
s
1
.
4
1
0
.
1
5
m
m
.
7
.
T
h
e
t
i
l
t
o
f
t
h
e
e
f
f
e
c
t
i
v
e
i
m
a
g
e
a
r
e
a
r
e
l
a
t
i
v
e
t
o
t
h
e
b
o
t
t
o
m
"
C
"
i
s
l
e
s
s
t
h
a
n
6
0
m
.
8
.
T
h
e
t
h
i
c
k
n
e
s
s
o
f
t
h
e
c
o
v
e
r
g
l
a
s
s
i
s
0
.
7
5
m
m
,
a
n
d
t
h
e
r
e
f
r
a
c
t
i
v
e
i
n
d
e
x
i
s
1
.
5
.
C
e
n
t
e
r
o
f
t
h
e
p
a
c
k
a
g
e
:
T
h
e
c
e
n
t
e
r
i
s
h
a
l
f
w
a
y
b
e
t
w
e
e
n
t
w
o
p
a
i
r
s
o
f
o
p
p
o
s
i
t
e
s
i
d
e
s
,
a
s
m
e
a
s
u
r
e
d
f
r
o
m
"
B
"
,
"
B
'
"
.
0
.
3
C
~
~
A
B
~
B
'
~
~
P
A
C
K
A
G
E
M
A
T
E
R
I
A
L
L
E
A
D
T
R
E
A
T
M
E
N
T
L
E
A
D
M
A
T
E
R
I
A
L
P
A
C
K
A
G
E
W
E
I
G
H
T
C
e
r
a
m
i
c
G
O
L
D
P
L
A
T
I
N
G
4
2
A
L
L
O
Y
0
.
9
g
M
PDF 
ZIP