1
E02217-PS
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any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXD3412GA
96 pin LFLGA (Plastic)
Description
The CXD3412GA is a timing generator and CCD
signal processor IC for the ICX412 CCD image sensor.
Features
Timing generator functions
Horizontal drive frequency 22.5MHz
(base oscillation frequency 45MHz)
Supports frame readout/draft (sextuple speed)/
AF (auto focus)
High-speed/low-speed shutter function
Horizontal and vertical drivers for CCD image
sensor
CCD signal processor functions
Correlated double sampling
Programmable gain amplifier (PGA) allows gain
adjustment over a wide range (6 to +42dB)
10-bit A/D converter
Chip Scale Package (CSP):
CSP allows vast reduction in the CCD camera
block footprint
Applications
Digital still cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX412 (Type 1/1.8, 3240K pixels)
Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
Absolute Maximum Ratings
Supply voltage
V
DD
a, V
DD
b, V
DD
c, V
DD
d
V
SS
0.3 to +7.0
V
V
DD
e, V
DD
f, V
DD
g
V
SS
0.3 to +4.0
V
VL
10.0 to V
SS
V
VH
VL 0.3 to +26.0
V
Input voltage (analog)
V
IN
V
SS
0.3 to V
DD
+ 0.3
V
Input voltage (digital)
V
I
V
SS
0.3 to V
DD
+ 0.3
V
Output voltage
V
O1
V
SS
0.3 to V
DD
+ 0.3
V
V
O2
VL 0.3 to V
SS
+ 0.3
V
V
O3
VL 0.3 to VH + 0.3
V
Operating temperature
Topr
20 to +75
C
Storage temperature
Tstg
55 to +125
C
Recommended Operating Conditions
Supply voltage
V
DD
d
3.0 to 5.5
V
V
DD
a, V
DD
b, V
DD
c, V
DD
d,
V
DD
e, V
DD
f, V
DD
g
3.0 to 3.6
V
VM
0.0
V
VH
14.5 to 15.5
V
VL
7.0 to 8.0
V
Operating temperature
Topr
20 to +75
C
2
CXD3412GA
Block Diagram
C7
C3
A1
NC
A2
NC
D8
C2
D7
C1
B8
AV
DD3
B6
AV
DD4
B9
AV
SS3
A6
AV
SS4
C5
AV
SS5
A3
SCK2
A4
SSI2
B4
SEN2
A5
TEST3
C4
TEST4
B5
TEST5
E2
DV
DD1
F2
DV
SS3
F3
DV
DD2
E3
DV
SS1
F1
B3
DV
SS2
D0 (LSB)
Latch
Serial Port
Register
DAC
PGA
CDS
ADC
Preblanking
Dummy Pixel
Auto Zero
Pulse Generator
V Driver
Serial Port
Register
SSG
Black Level
Auto Zero
B2
D1
B1
D2
C3
D3
C2
D4
C1
D5
D3
D6
D2
D7
D1
D8
E1
D9 (MSB)
G1
ADCLKI
G2
CLPOBI
G3
CLPDMI
L3
V
SS4
H1
ADCLK
H2
CLPOB
H3
CLPDM
J3
V
SS5
L1
OSCI
K1
OSCO
J1
CKI
J2
CKO
K2
MCKO
N8
SNCSL
L2
SSI1
M6
VL
L4
VM
M5
VH
M9
WEN
N9
ID/EXP
J7
V
SS3
J9
H2
J8
H1
H9
V
DD3
K9
V
SS2
K8
RG
K7
V
DD2
H8
V
DD4
H7
XRS
G7
PBLK
G8
XSHD
G9
XSHP
F7
PBLKI
F8
XSHDI
E7
AV
SS2
F9
XSHPI
D9
AV
SS1
E8
AV
DD2
E9
AV
DD1
C9
CCDIN
C6
C9
A7
C8
B7
C7
A8
AV
SS6
A9
AV
DD5
C8
C4
M1
SCK1
N1
SEN1
N3
V
SS6
L7
V
SS1
K3
V
DD5
L9
V
DD1
M2
VD
N2
HD
N7
SUB
N4
V4
N6
V3B
V3A
L6
V2
M4
N5
V1B
M7
TEST2
M3
TEST1
M8
RST
L8
SSGSL
L5
V1A
Selector
Latch
Selector
1/2
3
CXD3412GA
Pin Configuration (Top View)
NC
D2
D5
D8
D9
DV
SS2
ADCLKI
ADCLK
CKI
OSCO
OSCI
SCK1
SEN1
A
B
C
D
E
F
G
H
J
K
L
M
N
NC
D1
D4
D7
DV
DD1
DV
SS3
CLPOBI
CLPOB
CKO
MCKO
SSI1
VD
HD
SCK2
D0
D3
D6
DV
SS1
DV
DD2
CLPDMI
CLPDM
V
SS5
V
DD5
V
SS4
TEST1
V
SS6
SSI2
SEN2
TEST4
VM
V2
V4
TEST3
TEST5
AV
SS5
V1A
VH
V1B
AV
SS4
AV
DD4
C9
V3A
VL
V3B
C8
C7
C3
C1
AV
SS2
PBLKI
PBLK
XRS
V
SS3
V
DD2
V
SS1
TEST2
SUB
AV
SS6
AV
DD3
C4
C2
AV
DD2
XSHDI
XSHD
V
DD4
H1
RG
SSGSL
RST
SNCSL
AV
DD5
AV
SS3
CCDIN
AV
SS
1
AV
DD1
XSHPI
XSHP
V
DD3
H2
V
SS2
V
DD1
WEN
ID/EXP
1
2
3
4
5
6
7
8
9
4
CXD3412GA
Pin Description
Pin
No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D7
D8
D9
E1
E2
E3
E7
Symbol
NC
NC
SCK2
SSI2
TEST3
AV
SS4
C8
AV
SS6
AV
DD5
D2
D1
D0
SEN2
TEST5
AV
DD4
C7
AV
DD3
AV
SS3
D5
D4
D3
TEST4
AV
SS5
C9
C3
C4
CCDIN
D8
D7
D6
C1
C2
AV
SS1
D9
DV
DD1
DV
SS1
AV
SS2
I/O
--
--
I
I
I
--
--
--
--
O
O
O
I
I
--
--
--
--
O
O
O
I
--
--
--
--
I
O
O
O
--
--
--
O
--
--
--
Description
No connected. (Open)
No connected. (Open)
CCD signal processor block serial interface clock input. (Schmitt trigger)
CCD signal processor block serial interface data input. (Schmitt trigger)
CCD signal processor block test input 3. Connect to DV
SS
.
CCD signal processor block analog GND.
Capacitor connection.
CCD signal processor block analog GND.
CCD signal processor block analog power supply.
ADC output.
ADC output.
ADC output (LSB).
CCD signal processor block serial interface enable input. (Schmitt trigger)
CCD signal processor block test input 5. Connect to DV
DD
.
CCD signal processor block analog power supply.
Capacitor connection.
CCD signal processor block analog power supply.
CCD signal processor block analog GND.
ADC output.
ADC output.
ADC output.
CCD signal processor block test input 4. Connect to DV
SS
.
CCD signal processor block analog GND.
Capacitor connection.
Capacitor connection.
Capacitor connection.
CCD output signal input.
ADC output.
ADC output.
ADC output.
Capacitor connection.
Capacitor connection.
CCD signal processor block analog GND.
ADC output (MSB).
CCD signal processor block digital power supply. (Power supply for ADC)
CCD signal processor block digital GND. (GND for ADC)
CCD signal processor block analog GND.
5
CXD3412GA
Pin
No.
E8
E9
F1
F2
F3
F7
F8
F9
G1
G2
G3
G7
G8
G9
H1
H2
H3
H7
H8
H9
J1
J2
J3
J7
J8
J9
K1
K2
K3
K7
K8
K9
L1
L2
Symbol
AV
DD2
AV
DD1
DV
SS2
DV
SS3
DV
DD2
PBLKI
XSHDI
XSHPI
ADCLKI
CLPOBI
CLPDMI
PBLK
XSHD
XSHP
ADCLK
CLPOB
CLPDM
XRS
V
DD4
V
DD3
CKI
CKO
V
SS5
V
SS3
H1
H2
OSCO
MCKO
V
DD5
V
DD2
RG
V
SS2
OSCI
SSI1
I/O
--
--
--
--
--
I
I
I
I
I
I
O
O
O
O
O
O
O
--
--
I
O
--
--
O
O
O
O
--
--
O
--
I
I
Description
CCD signal processor block analog power supply.
CCD signal processor block analog power supply.
CCD signal processor block digital GND.
CCD signal processor block digital GND.
CCD signal processor block digital power supply.
Pulse input for horizontal and vertical blanking period pulse cleaning.
(Schmitt trigger)
CCD data level sample-and-hold pulse input. (Schmitt trigger)
CCD precharge level sample-and-hold pulse input. (Schmitt trigger)
Clock input for analog/digital conversion. (Schmitt trigger)
CCD optical black signal clamp pulse input. (Schmitt trigger)
CCD dummy signal clamp pulse input. (Schmitt trigger)
Pulse output for horizontal and vertical blanking period pulse cleaning.
CCD data level sample-and-hold pulse output.
CCD precharge level sample-and-hold pulse output.
Clock output for analog/digital conversion.
Logical phase can be adjusted by serial interface data.
CCD optical black signal clamp pulse output.
Horizontal/vertical OB pattern can be changed by serial interface data.
CCD dummy signal clamp pulse output.
Sample-and-hold pulse output for analog/digital conversion phase alignment.
Timing generator block digital power supply. (Power supply for CDS block)
Timing generator block 3.0 to 5.0V power supply. (Power supply for H1/H2)
Inverter input.
Inverter output.
Timing generator block digital GND.
Timing generator block digital GND.
CCD horizontal register clock output.
CCD horizontal register clock output.
Inverter output for oscillation. When not used, leave open or connect a capacitor.
System clock output for signal processor IC.
Timing generator block digital power supply. (Power supply for common logic block)
Timing generator block digital power supply. (Power supply for RG)
CCD reset gate pulse output.
Timing generator block digital GND.
Inverter input for oscillation. When not used, fix to low.
Timing generator block serial interface data input. Schmitt trigger input.
6
CXD3412GA
Pin
No.
L3
L4
L5
L6
L7
L8
L9
M1
M2
M3
M4
M5
M6
M7
M8
M9
N1
N2
N3
N4
N5
N6
N7
N8
N9
Symbol
V
SS4
VM
V1A
V3A
V
SS1
SSGSL
V
DD1
SCK1
VD
TEST1
V2
VH
VL
TEST2
RST
WEN
SEN1
HD
V
SS6
V4
V1B
V3B
SUB
SNCSL
ID/EXP
I/O
--
--
O
O
--
I
--
I
I/O
I
O
--
--
I
I
O
I
I/O
--
O
O
O
O
I
O
Description
Timing generator block digital GND.
Timing generator block digital GND. (GND for vertical driver)
CCD vertical register clock output.
CCD vertical register clock output.
Timing generator block digital GND.
Internal SSG enable.
High: Internal SSG valid, Low: External sync valid
(With pull-down resistor)
Timing generator block digital power supply. (Power supply for common logic block)
Timing generator block serial interface clock input.
Schmitt trigger input.
Vertical sync signal input/output.
Timing generator block test input 1.
Normally fix to GND.
(With pull-down resistor)
CCD vertical register clock output.
Timing generator block 15.0V power supply. (Power supply for vertical driver)
Timing generator block 7.5V power supply. (Power supply for vertical driver)
Timing generator block test input 2.
Normally fix to GND.
(With pull-down resistor)
Timing generator block reset input.
High: Normal operation, Low: Reset control
Normally apply reset during power-on.
Schmitt trigger input/No protective diode on power supply side.
Memory write timing pulse output.
Timing generator block serial interface strobe input.
Schmitt trigger input.
Horizontal sync signal input/output.
Timing generator block digital GND.
CCD vertical register clock output.
CCD vertical register clock output.
CCD vertical register clock output.
CCD electronic shutter pulse output.
Control input used to switch sync system.
High: CKI sync, Low: MCKO sync
(With pull-down resistor)
Vertical direction line identification pulse output/exposure time identification pulse
output.
Switching possible using the serial interface data. (Default: ID)
7
CXD3412GA
Electrical Characteristics
Timing Generator Block Electrical Characteristics
DC Characteristics
(Within the recommended operating conditions)
Item
Pins
Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply voltage 1
Supply voltage 2
Supply voltage 3
Supply voltage 4
Input
voltage 1
1
Input
voltage 2
2
Input/output
voltage
Output
voltage 1
Output
voltage 2
Output
voltage 3
Output
voltage 4
Output
voltage 5
Output
voltage 6
Output
current 1
Output
current 2
V
DD2
V
DD3
V
DD4
V
DD1
, V
DD5
RST, SSI1,
SCK1, SEN1
TEST1, TEST2,
SNCSL, SSGSL
VD, HD
H1, H2
RG
XSHP, XSHD,
XRS, PBLK,
CLPOB,
CLPDM,
ADCLK
CKO
MCKO
ID/EXP,
WEN
V1A, V1B,
V3A, V3B,
V2, V4
SUB
Feed current where I
OH
= 1.2mA
Pull-in current where I
OL
= 2.4mA
Feed current where I
OH
= 22.0mA
Pull-in current where I
OL
= 14.4mA
Feed current where I
OH
= 3.3mA
Pull-in current where I
OL
= 2.4mA
Feed current where I
OH
= 3.3mA
Pull-in current where I
OL
= 2.4mA
Feed current where I
OH
= 6.9mA
Pull-in current where I
OL
= 4.8mA
Feed current where I
OH
= 3.3mA
Pull-in current where I
OL
= 2.4mA
Feed current where I
OH
= 2.4mA
Pull-in current where I
OL
= 4.8mA
V1A/B, V2, V3A/B, V4 = 8.25V
V1A/B, V2, V3A/B, V4 = 0.25V
V1A/B, V3A/B = 0.25V
V1A/B, V3A/B = 14.75V
SUB = 8.25V
SUB = 14.75V
3.0
3.0
3.0
3.0
0.8V
DD
d
0.7V
DD
d
0.8V
DD
d
V
DD
d 0.8
V
DD
b 0.8
V
DD
a 0.8
V
DD
c 0.8
V
DD
d 0.8
V
DD
d 0.8
V
DD
d 0.8
10.0
5.0
5.4
3.3
3.3
3.3
3.3
3.6
5.25
3.6
3.6
0.2V
DD
d
0.3V
DD
d
0.2V
DD
d
0.4
0.4
0.4
0.4
0.4
0.4
0.4
5.0
7.2
4.0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
1
This input pin is a schmitt trigger input and it has protective diode of the power supply side in the IC.
It is not supported to 5V input.
2
These input pins are with pull-down resistor in the IC.
Note) This table indicates the conditions for 3.3V drive.
V
DD
a
V
DD
b
V
DD
c
V
DD
d
V
I+
V
I
V
IH1
V
IL1
V
IH2
V
IL2
V
OH1
V
OL1
V
OH2
V
OL2
V
OH3
V
OL3
V
OH4
V
OL4
V
OH5
V
OL5
V
OH6
V
OL6
V
OH7
V
OL7
I
OL
I
OM1
I
OM2
I
OH
I
OSL
I
OSH
8
CXD3412GA
Inverter I/O Characteristics for Oscillation
(Within the recommended operating conditions)
Item
Logical Vth
Input
voltage
Output
voltage
Feedback
resistor
Oscillation
frequency
Pins
OSCI
OSCI
OSCO
OSCI,
OSCO
OSCI,
OSCO
Symbol
LVth
V
IH
V
IL
V
OH
V
OL
RFB
f
Conditions
Feed current where I
OH
= 3.6mA
Pull-in current where I
OL
= 2.4mA
V
IN
= V
DD
d or V
SS
Min.
0.7V
DD
d
V
DD
d 0.8
500k
20
Typ.
V
DD
d/2
2M
Max.
0.3V
DD
d
0.4
5M
50
Unit
V
V
V
V
V
MHz
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Item
Logical Vth
Input
voltage
Input
amplitude
CKI
Symbol
LVth
V
IH
V
IL
V
IN
Conditions
fmax 50MHz sine wave
Min.
0.7V
DD
d
0.3
Typ.
V
DD
d/2
Max.
0.3V
DD
d
Unit
V
V
V
Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source.
Input amplitude is the input amplitude characteristics in the case of input through a capacitor.
Switching Characteristics
(VH = 15.0V, VM = GND, VL = 7.5V)
Item
Rise time
Fall time
Output noise voltage
Symbol
TTLM
TTMH
TTLH
TTML
TTHM
TTHL
VCLH
VCLL
VCMH
VCML
Conditions
VL to VM
VM to VH
VL to VH
VM to VL
VH to VM
VH to VL
Min.
200
200
30
200
200
30
Typ.
350
350
60
350
350
60
Max.
500
500
90
500
500
90
1.0
1.0
1.0
1.0
Unit
ns
ns
ns
ns
ns
ns
V
V
V
V
Notes)
1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1F or more) between
each power supply pin (VH, VL) and GND.
3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor.
Pins
9
CXD3412GA
Switching Waveforms
Waveform Noise
VCMH
VCML
VM
VL
VCLH
VCLL
V1A (V1B, V3A, V3B)
V2 (V4)
SUB
TTMH
TTHM
VH
VM
VL
VM
VL
VH
VL
90%
10%
90%
10%
TTLM
TTLM
90%
10%
90%
10%
TTLH
TTHL
90%
90%
10%
10%
TTML
90%
10%
TTML
90%
10%
10
CXD3412GA
Measurement Circuit
C1: 3300pF
C2: 560pF
C3: 820pF
C4: 8pF
C5: 215pF
C6: 10pF
R1: 30
R2: 10
N1
N2
L4
L5
L6
N7
L7
N8
N9
M1
M2
M3
N4
N5
N6
M4
N3 L2 K2 K9 K8 K7 K1 L1 K3 J9 J8 J7 J3 J2 J1 H9 H8 H7 H3 H2 L3 G9 G8 G7
A2 A1 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B9 B8 C1 C2 C3 C4 C5 C6
M5
M6
E1
L8
L9
M7
M8
M9
E8
D8
D7
D3
D2
D1
C9
C8
C7
F3
F2
G1
E9
D9
E7
G3
G2
H1
F9
F8
F7
F1
E3
E2
VD
CXD3412GA
V2
VH
VL
D9
SSGSL
V
DD1
SCK1
VD
TEST1
V4
V1B
V3B
TEST2
RST
WEN
SEN1
HD
VM
V1A
V3A
SUB
V
SS1
SNCSL
ID/EXP
CLPDMI
CLPOBI
ADCLK
XSHPI
XSHDI
PBLKI
DV
DD2
DV
SS3
ADCLKI
AV
DD1
AV
SS1
AV
SS2
DV
SS2
DV
SS1
DV
DD1
AV
DD2
C2
C1
D6
D7
D8
CCDIN
C4
C3
V
SS6
SSI1
MCK
O
V
SS2
RG
V
DD2
OSCO
OSCI
V
DD5
H2
H1
V
SS3
V
SS5
CK
O
CKI
V
DD3
V
DD4
XRS
CLPDM
CLPOB
V
SS4
XSHP
XSHD
PBLK
NC
NC
SCK2
SSI2
TEST3
AV
SS4
C8
AV
SS6
AV
DD5
D2
D1
D0
SEN2
TEST5
AV
DD4
C7
AV
SS3
AV
DD3
D5
D4
D3
TEST4
AV
SS5
C9
Serial interface data
HD
+3.3V
+15.0V
7.5V
C2
C2
C2
C2
C2
R1
R1
R1
R2
R1
R1
R1
C2
C2
C2
C2
C2
C2
C2
C2
C2
C1
C1
C1
C1
C1
C1
C2
C3
CKI
C6
C4
C5 C5
C6
C6
11
CXD3412GA
AC Characteristics
AC characteristics between the serial interface clocks
Serial interface clock internal loading characteristics (1)
Be sure to maintain a constantly high SEN1 logic level near the falling edge of the HD in the horizontal
period during which V1A/B and V3A/B values take the ternary value and during that horizontal period.
(Within the recommended operating conditions)
SSI1
0.2V
DD
d
0.2V
DD
d
0.8V
DD
d
ts2
th1
ts1
ts3
0.8V
DD
d
0.8V
DD
d
SCK1
SEN1
SEN1
0.2V
DD
d
th1
Enlarged view
Example: During frame mode
0.2V
DD
d
ts1
0.2V
DD
d
V1A
VD
HD
HD
V1A
SEN1
0.8V
DD
d
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
SEN1 setup time, activated by the falling edge of HD
SEN1 hold time, activated by the falling edge of HD
Min.
0
113
Typ.
Max.
Unit
ns
s
Symbol
ts1
th1
ts2
ts3
Definition
SSI1 setup time, activated by the rising edge of SCK1
SSI1 hold time, activated by the rising edge of SCK1
SCK1 setup time, activated by the rising edge of SEN1
SEN1 setup time, activated by the rising edge of SCK1
Min.
20
20
20
20
Typ.
Max.
Unit
ns
ns
ns
ns
12
CXD3412GA
Serial interface clock internal loading characteristics (2)
Be sure to maintain a constantly high SEN1 logic level near the falling edge of VD.
(Within the recommended operating conditions)
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD3412GA at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD3412GA and controlled at the rising edge of SEN1. See "Description of Operation".
(Within the recommended operating conditions)
th1
0.2V
DD
d
ts1
0.2V
DD
d
VD
HD
VD
HD
SEN1
0.8V
DD
d
Enlarged view
Example: During frame mode
Symbol
ts1
th1
Definition
SEN1 setup time, activated by the falling edge of VD
SEN1 hold time, activated by the falling edge of VD
Min.
0
200
Typ.
Max.
Unit
ns
ns
Symbol
tpdPULSE
Definition
Output signal delay, activated by the rising edge of SEN1
Min.
15
Typ.
Max.
100
Unit
ns
0.8V
DD
d
SEN1
Output signal
tpdPULSE
13
CXD3412GA
RST loading characteristics
(Within the recommended operating conditions)
VD and HD phase characteristics
(Within the recommended operating conditions)
RST
0.2V
DD
d
tw1
0.2V
DD
d
VD
HD
ts1
th1
0.2V
DD
d
0.2V
DD
d
0.2V
DD
d
Symbol
ts1
th1
Definition
VD setup time, activated by the falling edge of HD
VD hold time, activated by the falling edge of HD
Min.
0
0
Typ.
Max.
Unit
ns
ns
Symbol
tw1
Definition
RST pulse width
Min.
28
Typ.
Max.
Unit
ns
HD loading characteristics
MCKO load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
HD setup time, activated by the rising edge of MCKO
HD hold time, activated by the rising edge of MCKO
Min.
20
0
Typ.
Max.
Unit
ns
ns
HD
MCKO
ts1
th1
0.2V
DD
d
0.8V
DD
d
0.2V
DD
d
14
CXD3412GA
Output variation characteristics
WEN and ID/EXP load capacitance = 10pF
(Within the recommended operating conditions)
0.8V
DD
d
MCKO
WEN, ID/EXP
tpd1
Symbol
tpd1
Definition
Time until the above outputs change after the rise of MCKO
Min.
25
Typ.
Max.
70
Unit
ns
15
CXD3412GA
CCD Signal Processor Block Electrical Characteristics
DC Characteristics
(Fc = 22.5MSPS, DV
DD1, 2
= AV
DD1, 2, 3, 4, 5
= 3.3V, Ta = 25C)
Item
Supply voltage 1
Supply voltage 2
Supply voltage 3
Analog input
capacitance
Input voltage
A/D clock duty
Output voltage
Pins
DV
DD1
DV
DD2
AV
DD1
,
AV
DD2
,
AV
DD3
,
AV
DD4
,
AV
DD5
CCDIN
SCK2, SSI2,
SEN2, TEST3,
TEST4, XSHDI,
XSHPI, ADCLKI,
CLPOBI,
CLPDMI, PBLKI
ADCLKI
D0 to D9
Symbol
V
DD
e
V
DD
f
V
DD
g
C
IN
V
I+
V
I
V
OH
V
OL
Conditions
Feed current where I
OH
= 2.0mA
Pull-in current where I
OL
= 2.0mA
Min.
3.0
3.0
3.0
V
DD
e 0.9
Typ.
3.3
3.3
3.3
15
1.8
1.1
50
Max.
3.6
3.6
3.6
0.4
Unit
V
V
V
pF
V
V
%
V
V
Analog Characteristics
(Fc = 22.5MSPS, DV
DD1, 2
= AV
DD1, 2, 3, 4, 5
= 3.3V, Ta = 25C)
Item
CCDIN input voltage amplitude
PGA maximum gain
PGA minimum gain
ADC resolution
ADC maximum conversion rate
ADC integral non-linearity error
ADC differential non-linearity error
Signal-to-noise ratio
CCDIN input voltage clamp level
CCD optical black signal clamp
level
Symbol
V
IN
Gmax
Gmin
Fc max
E
L
E
D
SNR
CLP
OB
Conditions
PGA gain = 0dB, output full scale
PGA gain setting data = "3FFh"
PGA gain setting data = "000h"
PGA gain = 0dB
PGA gain = 0dB
CCDIN input connected to GND
via a coupling capacitor
PGA gain = 0dB
OBLVL = "8h"
PGA gain = 0dB
Min.
900
22.5
Typ.
42
6
10
1.0
0.5
77
1.5
32
Max.
1100
Unit
mV
dB
dB
bit
MHz
LSB
LSB
dB
V
LSB
16
CXD3412GA
AC Characteristics
AC characteristics between the serial interface clocks
The setting values are reflected to the operation 6 ADCLKI clocks after the serial data is loaded at the rise
of SEN2.
(Fc = 22.5MSPS, DV
DD1, 2
= AV
DD1, 2, 3, 4, 5
= 3.3V, Ta = 25C)
Symbol
tp1
ts1
th1
ts2
ts3
Definition
SCK2 clock period
SSI2 setup time, activated by the rise of SCK2
SSI2 hold time, activated by the rise of SCK2
SCK2 setup time, activated by the rise of SEN2
SEN2 setup time, activated by the rise of SCK2
Min.
100
30
30
30
30
Typ.
Max.
Unit
ns
ns
ns
ns
ns
SSI2
0.2V
DD
0.2V
DD
0.8V
DD
ts2
th1
ts1
ts3
0.8V
DD
0.8V
DD
SCK2
SEN2
SEN2
17
CXD3412GA
CDS/ADC Timing Chart
Set the input pulse polarity setting data D13, D14 and D15 of the serial interface data to "0".
(Fc = 22.5MSPS, DV
DD1, 2
= AV
DD1, 2, 3, 4, 5
= 3.3V, Ta = 25C)
Preblanking Timing Chart
Symbol
tw1
DL
Definition
ADCLKI clock period
ADCLKI clock duty
Data latency
Min.
44
Typ.
Max.
Unit
ns
%
clocks
50
9
N
N + 1
N 10
CCDIN
XSHPI
XSHDI
ADCLKI
D0 to D9
N 9
N 8
N 7
tw1
DL
N + 2
N + 3
11 Clocks
11 Clocks
PBLKI
ADCLKI
D0 to D9
All "0"
18
CXD3412GA
Description of Operation
Pulses output from the CXD3412GA's timing generator block are controlled mainly by the RST pin and by the
serial interface data. The Pin Status Table is shown below, and the details of serial interface control are
described on page 20 and thereafter.
Pin Status Table
Pin
No.
Symbol
CAM
SLP
STB
RST
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D7
NC
NC
SCK2
SSI2
TEST3
AV
SS4
C8
AV
SS6
AV
DD5
D2
D1
D0
SEN2
TEST5
AV
DD4
C7
AV
DD3
AV
SS3
D5
D4
D3
TEST4
AV
SS5
C9
C3
C4
CCDIN
D8
D7
D6
C1
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Pin
No.
Symbol
CAM
SLP
STB
RST
D8
D9
E1
E2
E3
E7
E8
E9
F1
F2
F3
F7
F8
F9
G1
G2
G3
G7
G8
G9
H1
H2
H3
H7
H8
H9
J1
J2
J3
J7
J8
C2
AV
SS1
D9
DV
DD1
DV
SS1
AV
SS2
AV
DD2
AV
DD1
DV
SS2
DV
SS3
DV
DD2
PBLKI
XSHDI
XSHPI
ADCLKI
CLPOBI
CLPDMI
PBLK
XSHD
XSHP
ADCLK
CLPOB
CLPDM
XRS
V
DD4
V
DD3
CKI
CKO
V
SS5
V
SS3
H1
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
ACT
L
L
H
ACT
L
L
ACT
ACT
L
L
ACT
ACT
L
L
ACT
ACT
L
L
H
ACT
L
L
H
ACT
L
L
ACT
--
--
ACT
ACT
ACT
ACT
ACT
ACT
L
ACT
--
--
ACT
L
L
ACT
19
CXD3412GA
Pin
No.
Symbol
CAM
SLP
STB
RST
J9
K1
K2
K3
K7
K8
K9
L1
L2
L3
L4
L5
L6
L7
L8
L9
M1
H2
OSCO
MCKO
V
DD5
V
DD2
RG
V
SS2
OSCI
SSI1
V
SS4
VM
V1A
V3A
V
SS1
SSGSL
V
DD1
SCK1
ACT
L
L
ACT
ACT
ACT
ACT
ACT
ACT
ACT
L
ACT
--
--
ACT
L
L
ACT
--
ACT
ACT
ACT
ACT
ACT
ACT
ACT
DIS
--
--
ACT
VH
VH
VM
ACT
VH
VH
VL
--
ACT
ACT
ACT
ACT
--
ACT
ACT
ACT
DIS
Pin
No.
Symbol
CAM
SLP
STB
RST
M2
M3
M4
M5
M6
M7
M8
M9
N1
N2
N3
N4
N5
N6
N7
N8
N9
VD
1
TEST1
V2
VH
VL
TEST2
RST
WEN
SEN1
HD
1
V
SS6
V4
V1B
V3B
SUB
SNCSL
ID/EXP
ACT
L
L
H
--
ACT
VM
VM
VM
--
--
--
ACT
ACT
ACT
L
ACT
L
L
L
ACT
ACT
ACT
DIS
ACT
L
L
H
--
ACT
VM
VM
VL
ACT
VH
VH
VM
ACT
VH
VH
VL
ACT
VH
VH
VL
ACT
ACT
ACT
ACT
ACT
L
L
L
1
It is for output. For input, all items are "ACT".
Note) ACT means that the circuit is operating, and DIS means that loading is stopped.
L indicates a low output level, and H a high output level in the controlled status.
Also, VH, VM and VL indicate the voltage levels applied to VH (Pin M5), VM (Pin L3) and VL (Pin M6),
respectively, in the controlled status.
20
CXD3412GA
Timing Generator Block Serial Interface Control
The CXD3412GA's timing generator block basically loads and reflects the timing generator block serial
interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion
specifies the horizontal period during which V1A/B and V3A/B, etc. take the ternary value.
Note that some items reflect the timing generator block serial interface data at the falling edge of VD or the
rising edge of SEN1.
There are two categories of timing generator block serial interface data: CXD3412GA timing generator block
drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data").
The details of each data are described below.
00
01
02
03
04
05
06
07
41
42
43
44
45
46
47
SSI1
SCK1
SEN1
21
CXD3412GA
Control Data
1
See D13 SMD.
2
See D32 FGOB.
Data
D00
to
D07
D08,
D09
D10
to
D12
D13
D14
D15
D16
to
D31
D32
D33
D34,
D35
D36,
D37
D38,
D39
D40
to
D47
Symbol
CHIP
CTG
MODE
SMD
HTSG
PTSG
--
FGOB
EXP
PTOB
LDAD
STB
--
Sunction
Chip enable
Category switching
Drive mode switching
Electronic shutter mode switching
1
HTSG control switching
1
Internal SSG function switching
--
Wide CLPOB generation switching
2
ID/EXP output switching
CLPOB waveform pattern switching
ADCLK logic phase switching
Standby control
--
Data = 0
Data = 1
10000001
Enabled
Other values
Disabled
See D08 to D09 CTG.
See D10 to D12 MODE.
See D34 to D35 PTOB.
See D36 to D37 LDAD.
See D38 to D39 STB.
OFF
OFF
NTSC equivalent
--
OFF
ID
--
ON
ON
PAL equivalent
--
ON
EXP
--
RST
All
0
All
0
All
0
0
0
0
All
0
0
0
All
0
1
0
All
0
All
0
22
CXD3412GA
Data
D00
to
D07
D08,
D09
D10
to
D19
D20
to
D31
D32
to
D41
D42
to
D47
Symbol
CHIP
CTG
SVD
SHD
SPL
--
Function
Chip enable
Category switching
Electronic shutter vertical period
specification
Electronic shutter horizontal period
specification
High-speed shutter position specification
--
Data = 0
Data = 1
10000001
Enabled
Other values
Disabled
See D08 to D09 CTG.
See D10 to D19 SVD.
See D20 to D31 SHD.
See D32 to D41 SPL.
--
Shutter Data
RST
All
0
All
0
All
0
All
0
All
0
All
0
23
CXD3412GA
Detailed Description of Each Data
Shared data: D08 , D09 CTG [Category]
Of the data provided to the CXD3412GA by the serial interface, the CXD3412GA loads D10 and subsequent
data to each data register as shown in the table below according to the conbination of D08 and D09 .
D09
0
0
1
D08
0
1
X
Description of operation
Loading to control data register
Loading to shutter data register
Test mode
Note that the CXD3412GA can apply these categories consecutively within the same vertical period. However,
care should be taken as the data is overwritten if the same category is applied.
Control data: D10 to D12 MODE [Drive mode]
The CXD3412GA timing generator block drive mode can be switched as follows. However, the drive mode bits
are loaded to the CXD3412GA and reflected at the falling edge of VD.
D12
0
0
0
0
1
1
D11
0
0
1
1
0
1
Description of operation
Draft mode (sextuple speed: default)
Frame mode (A field read out)
Frame mode (B field read out)
Frame mode
AF1 mode
AF2 mode
D10
0
1
0
1
X
X
Control data: D15 PTSG [Internal SSG output pattern]
The CXD3412GA internal SSG output pattern can be switched as follows. However, the internal SSG output
pattern bits are loaded to the CXD3412GA and reflected at the falling edge of VD.
D15
0
1
Description of operation
NTSC equivalent pattern output
PAL equivalent pattern output
VD period in each pattern is defined as follows. However, care should be taken that HD period is changing by
the mode.
See the Timing Charts for the actual operation.
NTSC equivalent pattern
PAL equivalent pattern
Frame mode
885H + 810ck
884H + 1104ck
Draft mode
285H + 1455ck
2
342H + 2592ck
AF1 mode
142H + 1384ck + 1383ck
171H + 1296ck
AF2 mode
71H + 1384ck
85H + 1960ck
24
CXD3412GA
Control data: D38 , D39 STB [Standby]
The operating mode is switched as follows. However, the standby bits are loaded to the CXD3412GA and
control is applied immediately at the rising edge of SEN1.
See the Pin Status Table for the pin status in each mode.
D39
X
0
1
D38
0
1
1
Operating mode
Normal operating mode
Sleep mode
Standby mode
Symbol
CAM
SLP
STB
Control data: D36 , D37 LDAD [ADCLK logic phase]
This indicates the ADCLK logic phase adjustment data. The default is 90 relative to MCKO.
D37
0
0
1
1
D36
0
1
0
1
Degree of adjustment ()
0
90
180
270
Control data: D34 , D35 PTOB [CLPOB waveform pattern]
This indicates the CLPOB waveform pattern. The default is "Normal".
D35
0
0
1
1
D34
0
1
0
1
Waveform pattern
(Normal)
(Shifted rearward)
(Shifted forward)
(Wide)
Control data: D32 FGOB [Wide CLPOB generation]
This controls wide CLPOB generation during the vertical OPB period. See the Timing Charts for the actual
operation. The default is "OFF".
D32
0
1
Description of operation
Wide CLPOB generation OFF
Wide CLPOB generation ON
25
CXD3412GA
Control data/shutter data: [Electronic shutter]
The CXD3412GA realizes various electronic shutter functions by using control data D13 SMD and D14
HTSG and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL.
These functions are described in detail below.
First, the various modes are shown below. These modes are switched using control data D13 SMD.
The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example.
However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC.
[Electronic shutter stopped mode]
During this mode, all shutter data items are invalid.
SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[Electronic shutter mode]
During this mode, the shutter data items have the following meanings.
Note) The bit data definition area is assured in terms of the CXD3412GA functions, and does not assure the
CCD characteristics.
The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure
time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the
operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors.
(Exposure time) = SVD + {(number of HD per 1V) (SHD + 1)}
Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed
shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this
period is finished.
The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of
horizontal periods applied to SHD can be considered as (number of SUB pulses 1).
MSB
D31
X
D30
0
D29
0
D28
1
D27
1
D26
1
D25
0
D24
0
LSB
1
C
SHD is expressed as 1C3h .
D23
0
D22
0
D21
1
D20
1
3
D13
0
1
Description of operation
Electronic shutter stopped mode
Electronic shutter mode
Symbol
SVD
SHD
SPL
Data
D10 to D19
D20 to D31
D32 to D41
Description
Number of vertical periods specification (000h
SVD
3FFh)
Number of horizontal periods specification (000h
SHD
7FFh)
Vertical period specification for high-speed shutter operation (000h
SPL
3FFh)
26
CXD3412GA
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the
low-speed shutter period.
In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD. At this time,
performing SPL > SVD setting applies to the state of SPL = SVD correspondingly.
Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed
shutter to high-speed shutter or vice-versa.
VD
SHD
1
V1A
SUB
WEN
SMD
000h
002h
SVD
050h
10Fh
SHD
1
SVD
EXP
Exposure time
VD
SPL
001
002
000
SHD
1
V1A
SUB
WEN
SMD
000h
001h
SPL
000h
002h
SVD
0A3h
10Fh
SHD
EXP
Exposure time
1
SVD
27
CXD3412GA
[HTSG control mode]
This mode controls the V1A/B and V3A/B ternary level outputs (readout pulse block) using D14 HTSG.
When control starts, V pulse modulation during readout period is not generated and the normal V transfer is
performed.
D14
0
1
Description of operation
Readout pulse (SG) normal operation
HTSG control mode
[EXP pulse]
The ID/EXP (Pin 9) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The
default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time
when it is high. In the draft mode, the transition point is the last SUB pulse falling edge, and midpoint value
(1443ck) of each V1A/B and V3A/B ternary output falling edge. When there is no SUB pulse, the later ternary
output falling edge (1538ck) is used. In the frame mode, the transition point is the last SUB pulse falling edge,
and each V1A/B and V3A/B ternary output falling edge (1348ck). When there is no SUB pulse, the V pulse
modulation falling edge just after ternary output (1386ck) is used. In addition, switching from ID to EXP is
performed at the timing (ID transition point of the horizontal period where V1A/B and V3A/B ternary output)
and reset to low.
See the EXP pulse indicated in the explanatory diagrams under Electronic Shutter for an image of operation.
VD
V1A
SUB
WEN
0
1
0
HTSG
1
0
1
SMD
VCK
Exposure time
EXP
28
CXD3412GA
Chart-1
Vertical Direction Timing Chart
MODE
Frame mode
Applicable CCD image sensor
ICX412
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
1560 stages are fixed for high-speed sweep block.
VD of this chart is NTSC equivalent pattern (885H + 810ck units). For PAL equivalent pattern, it is 884H + 1104ck units.
VD
SUB
CLPOB
CLPDM
V1A
C
High-speed sweep block
High-speed sweep block
C
V1B
V2
V3A
V3B
V4
CCD OUT
1542
1544
1546
1548
1550
1543
1545
1547
1549
1 3
2 4 6 8
4
2
6 8 10
5 7 1 3 5 7 9 11
PBLK
Wide CLPOB
ID/EXP
WEN
A Field
B Field
HD
1
1
886
877
877
886
A
B
96
95
101
101
29
CXD3412GA
Chart-2
Vertical Direction Timing Chart
MODE
Draft mode
Applicable CCD image sensor
ICX412
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
VD of this chart is NTSC equivalent pattern (285H + 1455ck + 1455ck units). For PAL equivalent pattern, it is 342H + 2592ck units.
VD
HD
SUB
V1A
V2
V3A
V3B
V4
Wide CLPOB
CLPDM
ID/EXP
PBLK
V1B
CCD OUT
10
3
6
15 22 27
8
1
4
13 20 25
30
28
3
6
10 15 22 27
1
4
8 13 20 25
30
28
WEN
CLPOB
1534
1527
1532
1525
1546
1539
1544
1549
1537
1534
1527
1532
1525
1546
1539
1544
1549
1537
287
287
260
1 2
260
2
1
D
D
30
CXD3412GA
Chart-3
Vertical Direction Timing Chart
MODE
AF1 mode
Applicable CCD image sensor
ICX412
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
75 stages are fixed for high-speed sweep block; 68 stages are fixed for frame shift block.
VD of this chart is NTSC equivalent pattern (142H + 1384ck + 1383ck units). For PAL equivalent pattern, it is 171H + 1296ck units.
High-speed sweep block starts from 159H.
VD
SUB
CLPOB
CLPDM
V1A
Frame shift block
V1B
V2
V3A
V3B
V4
CCD OUT
PBLK
ID/EXP
WEN
HD
6
4
6
4
D
E
E
E
D
E
144
144
Wide CLPOB
High-speed
sweep block
Frame shift block
High-speed
sweep block
1119
1114
1117
1112
430
423
428
421
442
435
440
433
430
423
428
421
442
435
440
433
1119
1114
1117
1112
131
2
14
131
2
14
31
CXD3412GA
Chart-4
Vertical Direction Timing Chart
MODE
AF2 mode
Applicable CCD image sensor
ICX412
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
116 stages are fixed for high-speed sweep block; 110 stages are fixed for frame shift block.
VD of this chart is NTSC equivalent pattern (71H + 1384ck units). For PAL equivalent pattern, it is 85H + 1960ck units.
High-speed sweep block starts from 68H. However, in this case, NTSC equivalent pattern frame rate is 0.5ck longer than 1/120s.
VD
SUB
CLPOB
CLPDM
V1A
V1B
V2
V3A
V3B
V4
CCD OUT
PBLK
ID/EXP
WEN
HD
6
4
6
4
D
E
E
E
D
E
72
72
Wide CLPOB
867
862
865
860
682
675
680
673
694
687
692
685
682
675
680
673
694
687
692
685
867
862
865
860
54
2
21
54
2
21
Frame shift block
High-speed
sweep block
Frame shift block
High-speed
sweep block
32
CXD3412GA
Chart-5
Horizontal Direction Timing Chart
MODE
Frame mode
Applicable CCD image sensor
ICX412
The HD of this chart indicates the actual CXD3412GA load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5s). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1.
CLPOB (wide) is output at the timing shown above at the position shown in Chart-1.
HD
MCKO
H1
H2
V1A/B
V2
V3A/B
V4
SUB
PBLK
CLPOB (1)
CLPOB (2)
CLPOB (3)
CLPOB (4)
CLPOB (wide)
CLPDM
(2544)
0
50
100
200
150
250
300
350
400
450
500
550
ID/EXP
WEN
428
456/460/464
52
4
276
162
42
16
34
8
50
8
458
50
50
24
454
430
352
238
314
124
454
52
390
200
120
52
124
124
33
CXD3412GA
Chart-6
Horizontal Direction Timing Chart
MODE
Draft mode, AF1 mode, AF2 mode
Applicable CCD image sensor
ICX412
The HD of this chart indicates the actual CXD3412GA load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5s). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4.
CLPOB (wide) is output at the timing shown above at the position shown in Chart-2, 3 and 4.
HD
MCKO
H1
H2
V1A/B
V2
V3A/B
V4
SUB
PBLK
CLPOB (1)
CLPOB (2)
CLPOB (3)
CLPOB (4)
CLPOB (wide)
CLPDM
(2624)
0
50
100
200
150
250
300
350
400
450
500
550
ID/EXP
WEN
508
536/540/544
52
4
140
42
16
34
8
50
8
538
50
50
24
534
510
172
204
534
52
156
120
52
124
124
268
188
300
220
252
124
284
236
396
316
348
380
332
412
364
444
476
460
492
428
34
CXD3412GA
Chart-7
Horizontal Direction Timing Chart
(High-speed sweep: C)
MODE
Frame mode
Applicable CCD image sensor
ICX412
The HD of this chart indicates the actual CXD3412GA load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5s). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID.
High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 93H 580ck (#1560).
HD
MCKO
H1
H2
V1A/B
V2
V3A/B
V4
SUB
PBLK
CLPOB
CLPDM
(2544)
0
50
100
200
150
250
300
350
400
450
500
550
ID/EXP
WEN
428
456/460/464
52
4
120
52
52
128
204
280
432
356
508
166
242
318
394
470
546
90
128
204
280
356
432
508
52
90
166
242
318
394
470
546
#4
#2
#3
#1
35
CXD3412GA
Chart-8
Horizontal Direction Timing Chart
(Frame shift, High-speed sweep: E)
MODE
AF1 mode, AF2 mode
Applicable CCD image sensor
ICX412
The HD of this chart indicates the actual CXD3412GA load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5s). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID. PBLK, CLPOB, ID/EXP and WEN are output at the timing shown above at the position shown in Chart-3 and 4.
Frame shift of V1A/B, V2, V3A/B and V4 is performed up to 11H 2548ck (#68) in AF1 mode and 18H 308ck (#110) in AF2 mode.
In addition, high-speed sweep is performed up to 141H 2612ck (#75) in AF1 mode and 70H 2612ck (#116) in AF2 mode.
HD
MCKO
H1
H2
V1A/B
V2
V3A/B
V4
SUB
PBLK
CLPOB
CLPDM
(2624)
0
50
100
200
150
250
300
350
400
450
500
550
ID/EXP
WEN
508
536/540/544
52
4
120
52
52
52
42
16
124
132
180
260
308
388
436
516
148
228
276
356
404
484
532
100
116
196
244
324
372
452
500
68
84
164
242
292
340
420
468
548
#2
#1
36
CXD3412GA
Chart-9
Horizontal Direction Timing Chart
MODE
Frame mode
Applicable CCD image sensor
ICX412
The HD of this chart indicates the actual CXD3412GA load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5s). Internal SSG is at this timing.
HD
[A Field]
[B Field]
[A]
[B]
V3B
V4
V3B
V4
V1A
V1B
V2
V3A
V1A
V1B
V2
V3A
(2544)
0
(2544)
0
1196
1234
1272
1310
1348
1386
124
162
200
238
276
314
352
390
37
CXD3412GA
Chart-10 Horizontal Direction Timing Chart
MODE
Draft mode, AF1 mode, AF2 mode
Applicable CCD image sensor
ICX412
The HD of this chart indicates the actual CXD3412GA load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5s). Internal SSG is at this timing.
HD
[D]
V3B
V4
V1A
V1B
V2
V3A
(2624)
0
(2544)
0
1158
1196
1234
1272
1310
1348
1386
1424
1462
1500
1538
1576
124
156
188
220
252
284
316
348
380
412
444
476
140
172
204
236
268
300
332
364
396
428
460
492
1592
1608
1640
1672
1624
1656
1688
38
CXD3412GA
Chart-11 High-Speed Phase Timing Chart
MODE
Applicable CCD image sensor
ICX412
HD' indicates the HD which is the actual CXD3412GA load timing.
The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse.
The logical phase of ADCLK can be specified by the serial interface data.
HD
HD'
CKI
CKO
ADCLK
MCKO
H1
H2
RG
XSHP
XSHD
XRS
428/508
52
1
39
CXD3412GA
Chart-12 Vertical Direction Sequence Chart
MODE
Draft
Frame
Draft
Applicable CCD image sensor
ICX412
This chart is a drive timing chart example of electronic shutter normal operation.
Data exposed at D includes a blooming component. For details, see the CCD image sensor data sheet.
The CXD3412GA does not generate the pulse to control mechanical shutter operation.
The switching timing of drive mode and electronic shutter data is not the same.
VD
V1A
V1B
V2
V3A
V3B
V4
SUB
Mechanical
shutter
Exposure
time
CCD OUT
MODE
SMD
SHD
Close
Open
A
B
C
E
E
F
0
0
0
0
0
3
0
0
1
1
1
1
1
0
1
1
050h
050h
050h
050h
050h
000h
3
0
000h
050h
050h
A
B
C
D
E
F
40
CXD3412GA
CCD Signal Processor Block Serial Interface Control
The CXD3412GA's CCD signal processor block basically loads the CCD signal processor block serial interface
data sent in the following format at the rising edge of SEN2, and the setting values are then reflected to the
operation 6 ADCLKI clocks after that.
CCD signal processor block serial interface control requires clock input to ADCLKI in order to load and reflect
the serial interface data to operation, so this should normally be performed when the timing generator block is
in the normal operation mode.
There are four categories of CCD signal processor block serial interface data: standby control data, PGA gain
setting data, OB clamp level setting data, and input pulse polarity setting data.
Note that when data from multiple categories is loaded consecutively, the data for the category loaded last is
valid and data from other categories is lost. When transferring data from multiple categories, raise SEN2 for
each category and wait until the setting value 6 ADCKLI clocks after that has been reflected to operation, then
transmit the next category.
The detail of each data are described below.
Standby Control Data
Data
D00
D01
to
D03
D04
to
D14
D15
Symbol
TEST
CTG
FIXED
STB
Function
Test code
Category switching
--
Standby control
Data = 0
Data = 1
Standby mode
Normal operation mode
Set to 0.
D01 to D03 CTG
Set to All 0.
Data
D00
D01
to
D03
D04,
D05
D06
to
D15
Symbol
TEST
CTG
FIXED
GAIN
Function
Test code
Category switching
--
PGA gain setting data
Data = 0
Data = 1
Set to 0.
D01 to D03 CTG
Set to All 0.
See D06 to D15 GAIN.
PGA Gain Setting Data
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
SSI2
SCK2
SEN2
41
CXD3412GA
Data
D00
D01
to
D03
D04
to
D11
D12
to
D15
Symbol
TEST
CTG
FIXED
OBLVL
Function
Test code
Category switching
--
OB clamp level setting data
Data = 0
Data = 1
Set to 0.
D01 to D03 CTG
Set to All 0.
See D12 to D15 OBLVL.
OB Clamp Level Setting Data
Data
D00
D01
to
D03
D04
to
D12
D13
to
D15
Symbol
TEST
CTG
FIXED
POL
Function
Test code
Category switching
--
Input pulse polarity setting data
Data = 0
Data = 1
Set to 0.
D01 to D03 CTG
Set to All 0.
Set to All 0.
Input Pulse Polarity Setting Data
42
CXD3412GA
Detailed Description of Each Data
Shared data: D01 to D03 CTG [Category]
Of the data provided to the CXD3412GA by the CCD signal processor block serial interface, the CXD3412GA
loads D04 and subsequent data to each data register as shown in the table below according to the
combination of D01 to D03 .
Standby control data: D15 STB [Standby]
The operating mode of the CCD signal processor block is switched as follows. When the CCD signal processor
block is in standby mode, only the serial interface is valid.
PGA gain setting data: D06 to D15 GAIN [PGA gain]
The CXD3412GA can set the programmable gain amplifier (PGA) gain from 6dB to +42dB in 1024 steps by
using PGA gain setting data D06 to D15 GAIN.
The PGA gain setting data is expressed as shown in the table below using D06 to D15 GAIN.
For example, when GAIN is set to "000h", "080h", "220h", "348h" and "3FFh", the respective PGA gain setting
values are 6dB, 0dB, +20dB, +34dB and +42dB.
MSB
D06
0
D07
1
D08
1
D09
1
D10
0
D11
0
D12
0
D13
0
D14
1
D15
1
LSB
1
C
3
GAIN is expressed as 1C3h .
D00
0
1
Description of operation
Normal operating mode
Standby mode
D01
0
0
0
0
1
D02
0
0
1
1
X
Description of operation
Loading to standby control data register
Loading to PGA gain setting data register
Loading to OB clamp level setting data register
Loading to input pulse polarity setting data register
Access prohibited
D03
0
1
0
1
X
43
CXD3412GA
OB clamp level setting data: D12 to D15 OBLVL [OB clamp output]
The CXD3412GA can set the OPB clamp output value from 0 to 60LSB in 4LSB steps by using CCD signal
processor block control data D12 to D15 OBLVL.
The OPB clamp output setting data is expressed as shown in the table below using D12 to D15 OBLVL.
For example, when OBLVL is set to "0h", "1h", "8h" and "Fh", the respective OPB clamp output setting values
are 0LSB, 4LSB, 32LSB and 60LSB.
D12
0
D13
1
D14
1
D15
0
LSB
6
MSB
OBLVL is expressed as 6h .
44
CXD3412GA
Application Circuit Block Diagram
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
SEN2
SCK2
SSI2
F9 F8 F7
G2
G3
G9 G8 G7
H2 H1
G1
B7
A7
C6
B3
A1
A2
B2
B1
C3
C2
C1
D3
D2
D1
E1
J2
K2
M2
N2
N9
M9
M8
N8
L8
M4
N5
L5
K8
J9
J8
C8
C7
D8
D7
C9
N4
L5
N7
N6
A3
B4
A4
M1
N1
L2
B5
C4
L1
J1
K1
A5
M7
M3
H3
CCD
ICX412
TG/CDS/PGA/ADC
CXD3412GA
Controller
SSI1
SEN1
SCK1
TEST5
TEST4
TEST3
TEST2
TEST1
OSCO
CKI
OSCI
D1
VD
HD
D0 (LSB)
Signal
Processor
Block
D2
NC
NC
D3
D4
D5
D6
D7
D8
D9 (MSB)
MCKO
CKO
SSGSL
SNCSL
RST
WEN
ID/EXP
0.1F
C7
XSHPI
XSHDI
PBLKI
CLPDMI
CLPOBI
XSHP
XSHD
PBLK
CLPDM
CLPOB
ADCLK
ADCLKI
0.1F
C8
0.1F
C9
1F
C1
1F
CCDIN
CCDOUT
390pF
C2
390pF
C3
240pF
C4
H1
H2
RG
V1A
V1B
V2
V3A
V3B
V4
SUB
This block diagram illustrates connections with each circuit
block, and is not an actual circuit diagram. See the CCD
image sensor data sheet for an example of specific circuit
connections with the CCD image sensor.
45
CXD3412GA
Notes on Operation
1. Be sure to start up the timing generator block VL and VH pin power supplies at the timing shown in the
figure below in order to prevent the SUB pin of the CCD image sensor from going to negative potential. In
addition, start up the timing generator block V
DD1
, V
DD2
, V
DD3
, V
DD4
and V
DD5
pin and CCD signal processor
block DV
DD1
, DV
DD2
, AV
DD1
, AV
DD2
, AV
DD3
, AV
DD4
and AV
DD5
pin power supplies at the same time either
before or at the same time as the VH pin power supply is started up.
2. Reset the timing generator block and CCD signal processor block during power-on. The timing generator
block is reset by inputting the reset signal to the RST pin. The CCD signal processor block is reset by
initializing the serial data.
3. Separate the timing generator block V
DD1
, V
DD2
, V
DD3
, V
DD4
and V
DD5
pins from the CCD signal processor
block DV
DD1
, DV
DD2
, AV
DD1
, AV
DD2
, AV
DD3
, AV
DD4
, and AV
DD5
pins.
Also, the ADC output driver stage is connected to the dedicated power supply pin DV
DD1
. Separating this pin
from other power supplies is recommended to avoid affecting the internal analog circuits.
4. The difference in potential between the timing generator block V
DD4
pin supply voltage 3 V
DD
c and the CCD
signal processor block DV
DD1
, DV
DD2
, AV
DD1
, AV
DD2
, AV
DD3
, AV
DD4
and AV
DD5
pin supply voltages 1 V
DD
e, 2
V
DD
f and 3 V
DD
g should be 0.1V or less.
5. The timing generator block and CCD signal processor block ground pins should use a shared ground which
is connected outside the IC. When the set ground is divided into digital and analog blocks, connect the
timing generator block ground pins to the digital ground and the CCD signal processor block ground pins to
the analog ground. The difference in potential between the timing generator block V
SS1
, V
SS2
, V
SS3
, V
SS4
,
V
SS5
, V
SS6
and VM and the CCD signal processor block DV
SS1
, DV
SS2
, DV
SS3
, AV
SS1
, AV
SS2
, AV
SS3
, AV
SS4
,
AV
SS5
and AV
SS6
should be 0.1V or less.
6. Do not perform serial communication with the CCD signal processor block during the effective image
period, as this may cause the picture quality to deteriorate. In addition, using SCK2, SSI2 and SEN2, which
are used by the CCD signal processor block, use of the dedicated ports is recommended. When using
these pins as shared ports with the timing generator block or other ICs, be sure to thoroughly confirm the
effects on picture quality before use.
t1
t2
15.0V
0V
7.5V
20%
20%
t2
t1
46
CXD3412GA
Sony Corporation
Package Outline Unit: mm
96PIN LFLGA
PACKAGE MASS
PACKAGE STRUCTURE
ORGANIC SUBSTRATE
0.3g
PACKAGE MATERIAL
TERMINAL TREATMENT
TERMINAL MATERIAL
SONY CODE
EIAJ CODE
JEDEC CODE
LFLGA-96P-02
P-LFLGA96-12X8-0.8
1.3 MAX
S
0.10
DETAIL X
S
S
0.2
PIN 1 INDEX
X
B
B
0.2
12.0
S
8.0
A
0.2
S
0.15
x4
0.8
B
D
E
F
G
H
J
K
L
C
A
M
N
1 2 3 4 5 6 7 8 9
0.8
M
S A B
96 -
0.45 0.05
A
0.5
0.5
3
0.50
0.5
0.9
0.9
1.2
0.8
0.10MAX
0.5
0.08
(0.3)
(0.3)
(0.3)
(0.3)
NICKEL & GOLD PLATING
COPPER
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