1/12
April 2001
s
HIGH SPEED:
f
MAX
= 300MHz (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 2
A(MAX.) at T
A
=25
C
s
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
s
50
TRANSMISSION LINE DRIVING
CAPABILITY
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74AC74 is an advanced high-speed CMOS
DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR
fabricated with sub-micron silicon gate
and double-layer metal wiring C
2
MOS tecnology.
A signal on the D INPUT is transferred to the Q
and Q OUTPUTS during the positive going
transition of the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
All
inputs
and
outputs
are
equipped
with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74AC74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
74AC74B
SOP
74AC74M
74AC74MTR
TSSOP
74AC74TTR
TSSOP
DIP
SOP
74AC74
2/12
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
PIN No
SYMBOL
NAME AND FUNCTION
1, 13
1CLR, 2CLR
Asynchronous Reset -
Direct Input
2, 12
1D, 2D
Data Inputs
3, 11
1CK, 2CK
Clock Input
(LOW to HIGH, Edge
Triggered)
4, 10
1PR, 2PR
Asynchronous Set - Direct
Input
5, 9
1Q, 2Q
True Flip-Flop Outputs
6, 8
1Q, 2Q
Complement Flip-Flop
Outputs
7
GND
Ground (0V)
14
V
CC
Positive Supply Voltage
INPUTS
OUTPUTS
FUNCTION
CLR
PR
D
CK
Q
Q
L
H
X
X
L
H
CLEAR
H
L
X
X
H
L
PRESET
L
L
X
X
H
H
H
H
L
L
H
H
H
H
H
L
H
H
X
Q
n
Q
n
NO CHANGE
74AC74
3/12
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
1) V
IN
from 30% to 70% of V
CC
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
50
mA
I
CC
or I
GND
DC V
CC
or Ground Current
200
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
2 to 6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time V
CC
= 3.0, 4.5 or 5.5V (note 1)
8
ns/V
74AC74
4/12
DC SPECIFICATIONS
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25
C
-40 to 85
C
-55 to 125
C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
3.0
V
O
= 0.1 V or
V
CC
-0.1V
2.1
1.5
2.1
2.1
V
4.5
3.15
2.25
3.15
3.15
5.5
3.85
2.75
3.85
3.85
V
IL
Low Level Input
Voltage
3.0
V
O
= 0.1 V or
V
CC
-0.1V
1.5
0.9
0.9
0.9
V
4.5
2.25
1.35
1.35
1.35
5.5
2.75
1.65
1.65
1.65
V
OH
High Level Output
Voltage
3.0
I
O
=-50
A
2.9
2.99
2.9
2.9
V
4.5
I
O
=-50
A
4.4
4.49
4.4
4.4
5.5
I
O
=-50
A
5.4
5.49
5.4
5.4
3.0
I
O
=-12 mA
2.56
2.46
2.4
4.5
I
O
=-24 mA
3.86
3.76
3.7
5.5
I
O
=-24 mA
4.86
4.76
4.7
V
OL
Low Level Output
Voltage
3.0
I
O
=50
A
0.002
0.1
0.1
0.1
V
4.5
I
O
=50
A
0.001
0.1
0.1
0.1
5.5
I
O
=50
A
0.001
0.1
0.1
0.1
3.0
I
O
=12 mA
0.36
0.44
0.5
4.5
I
O
=24 mA
0.36
0.44
0.5
5.5
I
O
=24 mA
0.36
0.44
0.5
I
I
Input Leakage
Current
5.5
V
I
= V
CC
or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
2
20
40
A
I
OLD
Dynamic Output
Current (note 1, 2)
5.5
V
OLD
= 1.65 V max
75
50
mA
I
OHD
V
OHD
= 3.85 V min
-75
-50
mA
74AC74
5/12
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
= 3ns)
(*) Voltage range is 3.3V
0.3V
(**) Voltage range is 5.0V
0.5V
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/2 (per
Fli p-Flop)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25
C
-40 to 85
C
-55 to 125
C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time CK to Q or Q
3.3
(*)
7.0
14.0
16.0
17.5
ns
5.0
(**)
5.0
10.0
10.5
12.0
t
PLH
t
PHL
Propagation Delay
Time PR or CLR to
Q or Q
3.3
(*)
6.0
12.0
13.5
14.0
ns
5.0
(**)
4.5
9.5
10.5
10.5
t
W
Pulse Width HIGH
or LOW, CK or PR
or CLR
3.3
(*)
5.0
1.5
7.0
7.0
ns
5.0
(**)
4.0
1.5
5.0
5.0
t
s
Setup Time D to CK
HIGH or LOW
3.3
(*)
4.0
-0.2
4.0
4.0
ns
5.0
(**)
3.0
-0.2
3.0
3.0
t
h
Hold Time D to CK
HIGH or LOW
3.3
(*)
2.0
0.2
3.0
3.0
ns
5.0
(**)
2.0
0.2
3.0
3.0
t
REM
Removal Time
PR or CLR to CK
3.3
(*)
1.0
-1.0
1.0
1.0
ns
5.0
(**)
1.0
-0.7
1.0
1.0
f
MAX
Maximum Clock
Frequency
3.3
(*)
100
300
90
90
MHz
5.0
(**)
140
300
130
130
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25
C
-40 to 85
C
-55 to 125
C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
5.0
3
pF
C
PD
Power Dissipation
Capacitance
(note 1)
5.0
f
IN
= 10MHz
35
pF
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