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February 2003
s
HIGH SPEED: t
PD
= 5.3ns (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 8
A(MAX.) at T
A
=25C
s
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX.)
s
50
TRANSMISSION LINE DRIVING
CAPABILITY
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT16373 is an advanced high-speed
CMOS
16-BIT
D-TYPE
LATCH
(3-STATE)
fabricated
with
sub-micron silicon gate and
double-layer metal wiring C
2
MOS tecnology.
This 16 bit D-Type latch is controlled by two latch
enable inputs (LE) and two output enable inputs
(OE). The device can be used as two 8-bit latches
or one 16-bit latch.
While the LE input is held at a high level, the Q
outputs will follow the data inputs precisely. When
the LE is taken low, the Q outputs will be latched
precisely at the levels set up at the D inputs. While
the (OE) input is low, the outputs will be in a
normal logic state (high or low logic level) and
while OE is in high level the outputs will be in a
high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All
inputs
and
outputs
are
equipped
with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ACT16373
16-BIT D-TYPE LATCH
WITH 3-STATE OUTPUTS (NON INVERTED)
ORDER CODES
PACKAGE
TUBE
T & R
TSSOP
74ACT16373TTR
TSSOP
PIN CONNECTION
74ACT16373
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INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don`t Care
Z : High Impedance
* : Q outputs are latched at the time when the LE input is taken low
logic level.
IEC LOGIC SYMBOLS
PIN No
SYMBOL
NAME AND FUNCTION
1
1OE
3 State Output Enable
Input (Active LOW)
2, 3, 5, 6, 8, 9,
11, 12
1Q0 to 1Q7 3-State Outputs
13, 14, 16, 17,
19, 20, 22, 23
2Q0 to 2Q7 3-State Outputs
24
2OE
3 State Output Enable
Input (Active LOW)
25
2LE
Latch Enable Input
36, 35, 33, 32,
30, 29, 27, 26
2D0 to 2D7 Data Inputs
47, 46, 44, 43,
41, 40, 38, 37
1D0 to 1D7 Data Inputs
48
1LE
Latch Enable Input
4, 10, 15, 21,
28, 34, 39, 45
GND
Ground (0V)
7, 18, 31, 42
V
CC
Positive Supply Voltage
INPUTS
OUTPUT
OE
LE
D
Q
H
X
X
Z
L
L
X
NO CHANGE *
L
H
L
L
L
H
H
H
74ACT16373
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LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
50
mA
I
CC
or I
GND
DC V
CC
or Ground Current
400
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
74ACT16373
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RECOMMENDED OPERATING CONDITIONS
1) V
IN
from 0.8V to 2.0V
DC SPECIFICATIONS
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time V
CC
= 4.5 to 5.5V (note 1)
8
ns/V
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
4.5
V
O
= 0.1 V or
V
CC
-0.1V
2.0
1.5
2.0
2.0
V
5.5
2.0
1.5
2.0
2.0
V
IL
Low Level Input
Voltage
4.5
V
O
= 0.1 V or
V
CC
-0.1V
1.5
0.8
0.8
0.8
5.5
1.5
0.8
0.8
0.8
V
V
OH
High Level Output
Voltage
4.5
I
O
=-50
A
4.4
4.49
4.4
4.4
5.5
I
O
=-50
A
5.4
5.49
5.4
5.4
4.5
I
O
=-24 mA
3.86
3.76
3.7
V
5.5
I
O
=-24 mA
4.86
4.76
4.7
V
OL
Low Level Output
Voltage
4.5
I
O
=50
A
0.001
0.1
0.1
0.1
5.5
I
O
=50
A
0.001
0.1
0.1
0.1
4.5
I
O
=24 mA
0.36
0.44
0.5
5.5
I
O
=24 mA
0.36
0.44
0.5
I
I
Input Leakage Cur-
rent
5.5
V
I
= V
CC
or GND
0.1
1
1
A
I
OZ
High Impedance
Output Leakege
Current
5.5
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
0.5
5
10
A
I
CCT
Max I
CC
/Input
5.5
V
I
= V
CC
- 2.1V
0.6
1.5
1.6
mA
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
8
80
160
A
I
OLD
Dynamic Output
Current (note 1, 2)
5.5
V
OLD
= 1.65 V max
75
50
mA
I
OHD
V
OHD
= 3.85 V min
-75
-50
mA
74ACT16373
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AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
= 3ns)
(*) Voltage range is 5.0V
0.5V
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/16 (per
circuit)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
Propagation Delay
Time LE to Q
5.0
(*)
4.2
6.5
12.8
13.7
ns
t
PHL
5.0
7.7
12.2
13.0
t
PLH
Propagation Delay
Time D to Q
5.0
(*)
4.1
6.3
11.1
11.8
ns
t
PHL
5.3
8.5
12.3
13.0
t
PZL
Output Enable
Time
5.0
(*)
5.7
6.5
14.2
15.1
ns
t
PZH
5.0
7.7
12.1
13.0
t
PLZ
Output Disable
Time
5.0
(*)
5.6
8.2
9.4
9.8
ns
t
PHZ
5.0
7.0
10.7
11.0
t
W(H)
LE Minimum Pulse
Width HIGH
5.0
(*)
2.2
1.7
2.6
2.6
ns
t
s
Setup Time D to
LE, HIGH or LOW
5.0
(*)
1.2
<1.0
1.4
1.4
ns
t
h
Hold Time D to LE,
HIGH or LOW
5.0
(*)
1.3
<1.0
1.6
1.6
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
5.0
3.5
pF
C
OUT
Output Capaci-
tance
5.0
11
pF
C
PD
Power Dissipation
Capacitance (note
1)
5.0
f
IN
= 10MHz
31
pF
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