1/11
April 2001
s
HIGH SPEED:
f
MAX
= 260MHz (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 4
A(MAX.) at T
A
=25C
s
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX.)
s
50
TRANSMISSION LINE DRIVING
CAPABILITY
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT374 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP-FLOP with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
These 8 bit D-Type Flip-Flop are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic that were setup at
the D inputs.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level); when
the OE is high the outputs go to the high
impedance state.
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ACT374
OCTAL D-TYPE FLIP-FLOP
WITH 3 STATE OUTPUTS (NON INVERTED)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
74ACT374B
SOP
74ACT374M
74ACT374MTR
TSSOP
74ACT374TTR
TSSOP
DIP
SOP
74ACT374
2/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
Z : High Impedance
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
PIN No
SYMBOL
NAME AND FUNCTION
1
OE
3-State Output Enable
(Active LOW)
2, 5, 6, 9, 12,
15, 16,19
Q0 to Q7
3-State Outputs
3, 4, 7, 8, 13,
14, 17, 18
D0 to D7
Data Inputs
11
CK
Clock Input (LOW-to-HIGH
Edge Trigger)
10
GND
Ground (0V)
20
V
CC
Positive Supply Voltage
INPUTS
OUTPUT
OE
CK
D
Q
H
X
X
Z
L
X
NO CHANGE
L
L
L
L
H
H
74ACT374
3/11
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
1) V
IN
from 0.8V to 2.0V
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
50
mA
I
CC
or I
GND
DC V
CC
or Ground Current
400
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time V
CC
= 4.5 to 5.5V (note 1)
8
ns/V
74ACT374
4/11
DC SPECIFICATIONS
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on trasmission lines with impedances as low as 50
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
= 3ns)
(*) Voltage range is 5.0V
0.5V
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
4.5
V
O
= 0.1 V or
V
CC
-0.1V
2.0
1.5
2.0
2.0
V
5.5
2.0
1.5
2.0
2.0
V
IL
Low Level Input
Voltage
4.5
V
O
= 0.1 V or
V
CC
-0.1V
1.5
0.8
0.8
0.8
5.5
1.5
0.8
0.8
0.8
V
V
OH
High Level Output
Voltage
4.5
I
O
=-50
A
4.4
4.49
4.4
4.4
5.5
I
O
=-50
A
5.4
5.49
5.4
5.4
4.5
I
O
=-24 mA
3.86
3.76
3.7
V
5.5
I
O
=-24 mA
4.86
4.76
4.7
V
OL
Low Level Output
Voltage
4.5
I
O
=50
A
0.001
0.1
0.1
0.1
5.5
I
O
=50
A
0.001
0.1
0.1
0.1
4.5
I
O
=24 mA
0.36
0.44
0.5
5.5
I
O
=24 mA
0.36
0.44
0.5
I
I
Input Leakage Cur-
rent
5.5
V
I
= V
CC
or GND
0.1
1
1
A
I
OZ
High Impedance
Output Leakege
Current
5.5
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
0.5
5
5
A
I
CCT
Max I
CC
/Input
5.5
V
I
= V
CC
- 2.1V
0.6
1.5
1.6
mA
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
4
40
80
A
I
OLD
Dynamic Output
Current (note 1, 2)
5.5
V
OLD
= 1.65 V max
75
50
mA
I
OHD
V
OHD
= 3.85 V min
-75
-50
mA
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time CK to Q
5.0
(*)
5.0
10.0
11.0
11.0
ns
t
PZL
t
PZH
Output Enable
Time
5.0
(*)
6.0
10.0
11.0
11.0
ns
t
PLZ
t
PHZ
Output Disable
Time
5.0
(*)
6.5
10.0
11.0
11.0
ns
t
W
CK Pulse Width
HIGH or LOW
5.0
(*)
1.5
5.0
5.0
5.0
ns
t
s
Setup Time D to
CK, HIGH or LOW
5.0
(*)
0.5
5.0
5.0
5.0
ns
t
h
Hold Time D to CK,
HIGH or LOW
5.0
(*)
-0.5
2.0
2.0
2.0
ns
f
MAX
Maximum CK
Frequency
5.0
(*)
100
260
85
85
MHz
74ACT374
5/11
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/n (per circuit)
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 500
or equivalent
R
T
= Z
OUT
of pulse generator (typically 50
)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
5.0
3
pF
C
OUT
Output
Capacitance
5.0
8
pF
C
PD
Power Dissipation
Capacitance (note
1)
5.0
f
IN
= 10MHz
25
pF
TEST
SWITCH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
2V
CC
t
PZH
, t
PHZ
Open
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