1/12
April 2001
s
HIGH SPEED:
f
MAX
= 250MHz (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 4
A(MAX.) at T
A
=25C
s
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX.)
s
50
TRANSMISSION LINE DRIVING
CAPABILITY
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT74 is an advanced high-speed CMOS
DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C
2
MOS tecnology.
A signal on the D INPUT is transferred to the Q
and Q OUTPUTS during the positive going
transition of the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ACT74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
74ACT74B
SOP
74ACT74M
74ACT74MTR
TSSOP
74ACT74TTR
TSSOP
DIP
SOP
74ACT74
2/12
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
PIN No
SYMBOL
NAME AND FUNCTION
1, 13
1CLR, 2CLR
Asyncronous Reset -
Direct Input
2, 12
1D, 2D
Data Inputs
3, 11
1CK, 2CK
Clock Input
(LOW to HIGH, Edge
Triggered)
4, 10
1PR, 2PR
Asyncronous Set - Direct
Input
5, 9
1Q, 2Q
True Flip-Flop Outputs
6, 8
1Q, 2Q
Complement Flip-Flop
Outputs
7
GND
Ground (0V)
14
V
CC
Positive Supply Voltage
INPUTS
OUTPUTS
FUNCTION
CLR
PR
D
CK
Q
Q
L
H
X
X
L
L
CLEAR
H
L
X
X
H
L
PRESET
L
L
X
X
H
H
H
H
L
L
H
H
H
H
H
L
H
H
X
Q
n
Q
n
NO CHANGE
74ACT74
3/12
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
1) V
IN
from 0.8V to 2.0V
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
50
mA
I
CC
or I
GND
DC V
CC
or Ground Current
200
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time V
CC
= 4.5 to 5.5V (note 1)
8
ns/V
74ACT74
4/12
DC SPECIFICATIONS
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
= 3ns)
(*) Voltage range is 5.0V
0.5V
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
4.5
V
O
= 0.1 V or
V
CC
-0.1V
2.0
1.5
2.0
2.0
V
5.5
2.0
1.5
2.0
2.0
V
IL
Low Level Input
Voltage
4.5
V
O
= 0.1 V or
V
CC
-0.1V
1.5
0.8
0.8
0.8
5.5
1.5
0.8
0.8
0.8
V
V
OH
High Level Output
Voltage
4.5
I
O
=-50
A
4.4
4.49
4.4
4.4
5.5
I
O
=-50
A
5.4
5.49
5.4
5.4
4.5
I
O
=-24 mA
3.86
3.76
3.7
V
5.5
I
O
=-24 mA
4.86
4.76
4.7
V
OL
Low Level Output
Voltage
4.5
I
O
=50
A
0.001
0.1
0.1
0.1
5.5
I
O
=50
A
0.001
0.1
0.1
0.1
4.5
I
O
=24 mA
0.36
0.44
0.5
5.5
I
O
=24 mA
0.36
0.44
0.5
I
I
Input Leakage Cur-
rent
5.5
V
I
= V
CC
or GND
0.1
1
1
A
I
CCT
Max I
CC
/Input
5.5
V
I
= V
CC
- 2.1V
0.6
1.5
1.6
mA
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
4
40
40
A
I
OLD
Dynamic Output
Current (note 1, 2)
5.5
V
OLD
= 1.65 V max
75
50
mA
I
OHD
V
OHD
= 3.85 V min
-75
-50
mA
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time CK to Q or Q
5.0
(*)
5.0
10.0
11.0
11.0
ns
t
PLH
t
PHL
Propagation Delay
Time PR or CLR to
Q or Q
5.0
(*)
5.0
10.0
11.0
11.0
ns
t
W
Pulse Width HIGH
or LOW, CK or PR
or CLR
5.0
(*)
1.5
5.0
6.0
6.0
ns
t
s
Setup Time D to CK
HIGH or LOW
5.0
(*)
0.5
3.0
3.5
3.5
ns
t
h
Hold Time D to CK
HIGH or LOW
5.0
(*)
-0.5
1.0
1.0
1.0
ns
t
REM
Removal Tim|
PR or CLR to CK
5.0
(*)
-0.7
1.0
1.0
1.0
ns
f
MAX
Maximum Clock
Frequency
5.0
(*)
100
250
85
85
MHz
74ACT74
5/12
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/2 (per
Flip-Flop)
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 500
or equivalent
R
T
= Z
OUT
of pulse generator (typically 50
)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
5.0
3
pF
C
PD
Power Dissipation
Capacitance (note
1)
5.0
f
IN
= 10MHz
43
pF
74ACT74
6/12
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
74ACT74
7/12
WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
74ACT74
8/12
WAVEFORM 3: RECOVERY TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 4: PULSE WIDTH
74ACT74
9/12
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
a1
0.51
0.020
B
1.39
1.65
0.055
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
15.24
0.600
F
7.1
0.280
I
5.1
0.201
L
3.3
0.130
Z
1.27
2.54
0.050
0.100
P001A
Plastic DIP-14 MECHANICAL DATA
74ACT74
10/12
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.75
0.068
a1
0.1
0.2
0.003
0.007
a2
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45 (typ.)
D
8.55
8.75
0.336
0.344
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
7.62
0.300
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
0.68
0.026
S
8 (max.)
P013G
SO-14 MECHANICAL DATA
74ACT74
11/12
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.1
0.433
A1
0.05
0.10
0.15
0.002
0.004
0.006
A2
0.85
0.9
0.95
0.335
0.354
0.374
b
0.19
0.30
0.0075
0.0118
c
0.09
0.20
0.0035
0.0079
D
4.9
5
5.1
0.193
0.197
0.201
E
6.25
6.4
6.5
0.246
0.252
0.256
E1
4.3
4.4
4.48
0.169
0.173
0.176
e
0.65 BSC
0.0256 BSC
K
0
o
4
o
8
o
0
o
4
o
8
o
L
0.50
0.60
0.70
0.020
0.024
0.028
c
E
b
A2
A
E1
D
1
PIN 1 IDENTIFICATION
A1
L
K
e
TSSOP14 MECHANICAL DATA
74ACT74
12/12
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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