1/9
September 2001
s
5V TOLERANT INPUTS AND OUTPUTS
s
HIGH SPEED :
t
PD
= 5.4 ns (MAX.) at V
CC
= 3V
s
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
s
PCI BUS LEVELS GUARANTEED AT 24 mA
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16373
s
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCX16373 is a low voltage CMOS 16 BIT
D-TYPE LATCH with 3 STATE OUTPUTS NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 16 bit D-TYPE latches are byte controlled
by two latch enable inputs (nLE) and two output
enable inputs(OE).
While the nLE input is held at a high level, the nQ
outputs will follow the data input precisely.
When the nLE is taken LOW, the nQ outputs will
be latched precisely at the logic level of D input
data.
While the (nOE) input is low, the nQ outputs will be
in a normal logic state (high or low logic level) and
while high level the outputs will be in a high imped-
ance state.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
74LCX16373
LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
ORDER CODES
PACKAGE
TUBE
T & R
TSSOP
74LCX16373TTR
TSSOP
PIN CONNECTION
74LCX16373
2/9
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don`t Care
Z : High Impedance
* : Q outputs are latched at the time when the LE input is taken low
logic level.
IEC LOGIC SYMBOLS
PIN No
SYMBOL
NAME AND FUNCTION
1
1OE
3 State Output Enable
Input (Active LOW)
2, 3, 5, 6, 8, 9,
11, 12
1Q0 to 1Q7 3-State Outputs
13, 14, 16, 17,
19, 20, 22, 23
2Q0 to 2Q7 3-State Outputs
24
2OE
3 State Output Enable
Input (Active LOW)
25
2LE
Latch Enable Input
36, 35, 33, 32,
30, 29, 27, 26
2D0 to 2D7 Data Inputs
47, 46, 44, 43,
41, 40, 38, 37
1D0 to 1D7 Data Inputs
48
1LE
Latch Enable Input
4, 10, 15, 21,
28, 34, 39, 45
GND
Ground (0V)
7, 18, 31, 42
V
CC
Positive Supply Voltage
INPUTS
OUTPUT
OE
LE
D
Q
H
X
X
Z
L
L
X
NO CHANGE *
L
H
L
L
L
H
H
H
74LCX16373
3/9
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I
O
absolute maximum rating must be observed
2) V
O
< GND
RECOMMENDED OPERATING CONDITIONS
1) Truth Table guaranteed: 1.5V to 3.6V
2) V
IN
from 0.8V to 2V at V
CC
= 3.0V
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage (OFF State)
-0.5 to +7.0
V
V
O
DC Output Voltage (High or Low State) (note 1)
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 50
mA
I
OK
DC Output Diode Current (note 2)
- 50
mA
I
O
DC Output Current
50
mA
I
CC
DC Supply Current per Supply Pin
100
mA
I
GND
DC Ground Current per Supply Pin
100
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage (note 1)
2.0 to 3.6
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage (OFF State)
0 to 5.5
V
V
O
Output Voltage (High or Low State)
0 to V
CC
V
I
OH
, I
OL
High or Low Level Output Current (V
CC
= 3.0 to 3.6V)
24
mA
I
OH
, I
OL
High or Low Level Output Current (V
CC
= 2.7V)
12
mA
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time (note 2)
0 to 10
ns/V
74LCX16373
4/9
DC SPECIFICATIONS
DYNAMIC SWITCHING CHARACTERISTICS
1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
-40 to 85
C
-55 to 125
C
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.7 to 3.6
2.0
2.0
V
V
IL
Low Level Input
Voltage
0.8
0.8
V
V
OH
High Level Output
Voltage
2.7 to 3.6
I
O
=-100
A
V
CC
-0.2
V
CC
-0.2
V
2.7
I
O
=-12 mA
2.2
2.2
3.0
I
O
=-18 mA
2.4
2.4
I
O
=-24 mA
2.2
2.2
V
OL
Low Level Output
Voltage
2.7 to 3.6
I
O
=100
A
0.2
0.2
V
2.7
I
O
=12 mA
0.4
0.4
3.0
I
O
=16 mA
0.4
0.4
I
O
=24 mA
0.55
0.55
I
I
Input Leakage
Current
2.7 to 3.6
V
I
= 0 to 5.5V
5
5
A
I
off
Power Off Leakage
Current
0
V
I
or V
O
= 5.5V
10
10
A
I
OZ
High Impedance
Output Leakage
Current
2.7 to 3.6
V
I
= V
IH
or V
IL
V
O
= 0 to V
CC
5
5
A
I
CC
Quiescent Supply
Current
2.7 to 3.6
V
I
= V
CC
or GND
20
20
A
V
I
or V
O
= 3.6 to 5.5V
20
20
I
CC
I
CC
incr. per Input
2.7 to 3.6
V
IH
= V
CC
- 0.6V
500
500
A
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25
C
Min.
Typ.
Max.
V
OLP
Dynamic Low Level Quiet
Output (note 1)
3.3
C
L
= 50pF
V
IL
= 0V, V
IH
= 3.3V
0.8
V
V
OLV
-0.8
74LCX16373
5/9
AC ELECTRICAL CHARACTERISTICS
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/16 (per
circuit)
Symbol
Parameter
Test Conditi on
Value
Unit
V
CC
(V)
C
L
(pF)
R
L
(
)
t
s
= t
r
(ns)
-40 to 85
C
-55 to 125
C
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time (Dn to Qn)
2.7
50
500
2.5
1.5
5.9
1.5
5.9
ns
3.0 to 3.6
1.5
5.4
1.5
5.4
t
PLH
t
PHL
Propagation Delay
Time (LE to Qn)
2.7
50
500
2.5
1.5
6.4
1.5
6.4
ns
3.0 to 3.6
1.5
5.5
1.5
5.5
t
PZL
t
PZH
Output Enable Time
to HIGH and LOW
level
2.7
50
500
2.5
1.5
6.5
1.5
6.5
ns
3.0 to 3.6
1.5
6.1
1.5
6.1
t
PLZ
t
PHZ
Output Disable Time
from HIGH to LOW
level
2.7
50
500
2.5
1.5
6.3
1.5
6.3
ns
3.0 to 3.6
1.5
6.0
1.5
6.0
t
S
Set-Up Time, HIGH
or LOW level
(Dn to LE)
2.7
50
500
2.5
2.5
2.5
ns
3.0 to 3.6
2.5
2.5
t
h
Hold Time, HIGH or
LOW level
(Dn to LE)
2.7
50
500
2.5
1.5
1.5
ns
3.0 to 3.6
1.5
1.5
t
W
LE Pulse Width,
HIGH
2.7
50
500
2.5
3.0
3.0
ns
3.0 to 3.6
3.0
3.0
t
OSLH
t
OSHL
Output To Output
Skew Time (note1,
2)
3.0 to 3.6
50
500
2.5
1.0
1.0
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25
C
Min.
Typ.
Max.
C
IN
Input Capacitance
3.3
V
IN
= 0 to V
CC
7
pF
C
OUT
Output Capacitance
3.3
V
IN
= 0 to V
CC
8
pF
C
PD
Power Dissipation Capacitance
(note 1)
3.3
f
IN
= 10MHz
V
IN
= 0 or V
CC
20
pF
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