1/9
July 2001
s
HIGH SPEED:
t
PD
= 5.5ns (TYP.) at V
CC
= 3.3 V
s
COMPATIBLE WITH TTL OUTPUTS
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
=25C
s
LOW NOISE:
V
OLP
= 0.2V (TYP.) at V
CC
= 3.3V
s
75
TRANSMISSION LINE DRIVING
CAPABILITY
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
s
PCI BUS LEVELS GUARANTEED AT 24 mA
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ138 is a low voltage CMOS 3 TO 8
LINE DECODER (INVERTING) fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is ideal for low power
and low noise 3.3V applications.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
Three enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ138
3 TO 8 LINE DECODER (INVERTING)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
74LVQ138M
74LVQ138MTR
TSSOP
74LVQ138TTR
TSSOP
SOP
74LVQ138
2/9
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
PIN No
SYMBOL
NAME AND FUNCTION
1, 2, 3
A, B, C
Address Inputs
4, 5
G2A, G2B
Enable Inputs
6
G1
Enable Input
15, 14, 13,
12, 11, 10, 9,
7
Y0 to Y7
Outputs
8
GND
Ground (0V)
16
V
CC
Positive Supply Voltage
INPUTS
OUTPUTS
ENABLE
SELECT
G2B
G2A
G1
C
B
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
X
L
X
X
X
H
H
H
H
H
H
H
H
X
H
X
X
X
X
H
H
H
H
H
H
H
H
H
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
H
L
L
L
L
H
H
H
H
H
H
H
L
L
H
L
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
L
H
H
L
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
L
L
H
H
L
L
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
74LVQ138
3/9
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
50
mA
I
CC
or I
GND
DC V
CC
or Ground Current
200
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage (note 1)
2 to 3.6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time V
CC
= 3.0V (note 2)
0 to 10
ns/V
74LVQ138
4/9
DC SPECIFICATIONS
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75
DYNAMIC SWITCHING CHARACTERISTICS
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
3.0 to
3.6
2.0
2.0
2.0
V
V
IL
Low Level Input
Voltage
0.8
0.8
0.8
V
V
OH
High Level Output
Voltage
3.0
I
O
=-50
A
2.9
2.99
2.9
2.9
V
I
O
=-12 mA
2.58
2.48
2.48
I
O
=-24 mA
2.2
2.2
V
OL
Low Level Output
Voltage
3.0
I
O
=50
A
0.002
0.1
0.1
0.1
V
I
O
=12 mA
0
0.36
0.44
0.44
I
O
=24 mA
0.55
0.55
I
I
Input Leakage
Current
3.6
V
I
= V
CC
or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
3.6
V
I
= V
CC
or GND
4
40
40
A
I
OLD
Dynamic Output
Current (note 1, 2)
3.6
V
OLD
= 0.8 V max
36
25
mA
I
OHD
V
OHD
= 2 V min
-25
-25
mA
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
3.3
C
L
= 50 pF
0.2
0.8
V
V
OLV
-0.8
-0.2
V
IHD
Dynamic High
Voltage Input (note
1, 3)
3.3
2
V
V
ILD
Dynamic Low
Voltage Input (note
1, 3)
3.3
0.8
V
74LVQ138
5/9
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
= 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= |t
PLHm
- t
PLHn
|, t
OSHL
= |t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
0.3V
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= 500
or equivalent
R
T
= Z
OUT
of pulse generator (typically 50
)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time
A, B, C to Y
2.7
6.6
10.5
12.0
14.0
ns
3.3
(*)
5.5
8.0
9.0
10.5
t
PLH
t
PHL
Propagation Delay
Time
G1 to Y
2.7
6.7
10.5
12.0
14.0
ns
3.3
(*)
5.6
8.0
9.0
10.5
t
PLH
t
PHL
Propagation Delay
Time
G2A or G2B to Y
2.7
6.3
10.5
12.0
14.0
ns
3.3
(*)
5.2
8.0
9.0
10.5
t
OSLH
t
OSHL
Output To Output
Skew Time
(note1, 2)
2.7
0.5
1.0
1.0
1.0
ns
3.3
(*)
0.5
1.0
1.0
1.0
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
3.3
4
pF
C
PD
Power Dissipation
Capacitance (note
1)
3.3
f
IN
= 10MH
50
pF
74LVQ138
6/9
WAVEFORM 1 : PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz; 50% duty
cycle)
74LVQ138
7/9
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
1.75
0.068
a1
0.1
0.2
0.003
0.007
a2
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45 (typ.)
D
9.8
10
0.385
0.393
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
0.62
0.024
S
8 (max.)
SO-16 MECHANICAL DATA
PO13H
74LVQ138
8/9
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
1.2
0.047
A1
0.05
0.15
0.002
0.004
0.006
A2
0.8
1
1.05
0.031
0.039
0.041
b
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0089
D
4.9
5
5.1
0.193
0.197
0.201
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
e
0.65 BSC
0.0256 BSC
K
0
8
0
8
L
0.45
0.60
0.75
0.018
0.024
0.030
TSSOP16 MECHANICAL DATA
c
E
b
A2
A
E1
D
1
PIN 1 IDENTIFICATION
A1
L
K
e
0080338D
74LVQ138
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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