1/10
July 2001
s
HIGH SPEED:
t
PD
=5.8ns (TYP.) at V
CC
= 3.3V
s
5V TOLERANT INPUTS
s
POWER-DOWN PROTECTION ON INPUTS
s
INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
=3V
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
=25
C
s
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
=3.3V
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN) at V
CC
=3V
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX373 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All
inputs
and
outputs
are
equipped
with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX373
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
74LVX373M
74LVX373MTR
TSSOP
74LVX373TTR
TSSOP
SOP
74LVX373
2/10
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
Z : High Impedance
* : Q Outputs are Latched at the time when the LE INPUT is taken low logic level
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
PIN No
SYMBOL
NAME AND FUNCTION
1
OE
3 State Output Enable
Input (Active LOW)
3, 4, 7, 8, 13,
14, 17, 18
D0 to D7
Data Inputs
2, 5, 6, 9, 12,
15, 16,19
Q0 to Q7
3-State Outputs
11
LE
Latch Enable Input
10
GND
Ground (0V)
20
V
CC
Positive Supply Voltage
INPUTS
OUTPUT
OE
LE
D
Q
H
X
X
Z
L
L
X
NO CHANGE*
L
H
L
L
L
H
H
H
74LVX373
3/10
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2.0V
DC SPECIFICATIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage (note 1)
2 to 3.6
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time (note 2) (V
CC
= 3V)
0 to 100
ns/V
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25
C
-40 to 85
C
-55 to 125
C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
3.0
2.0
2.0
2.0
3.6
2.4
2.4
2.4
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
V
3.0
0.8
0.8
0.8
3.6
0.8
0.8
0.8
V
OH
High Level Output
Voltage
2.0
I
O
=-50
A
1.9
2.0
1.9
1.9
V
3.0
I
O
=-50
A
2.9
3.0
2.9
2.9
3.0
I
O
=-4 mA
2.58
2.48
2.4
V
OL
Low Level Output
Voltage
2.0
I
O
=50
A
0.0
0.1
0.1
0.1
V
3.0
I
O
=50
A
0.0
0.1
0.1
0.1
3.0
I
O
=4 mA
0.36
0.44
0.55
I
OZ
High Impedance
Output Leakage
Current
3.6
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
0.25
2.5
5
A
I
I
Input Leakage
Current
3.6
V
I
= 5V or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
3.6
V
I
= V
CC
or GND
4
40
40
A
74LVX373
4/10
DYNAMIC SWITCHING CHARACTERISTICS
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
0.3V
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25
C
-40 to 85
C
-55 to 125
C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
3.3
C
L
= 50 pF
0.3
0.8
V
V
OLV
-0.8
-0.3
V
IHD
Dynamic High
Voltage Input
(note 1, 3)
3.3
2.0
V
ILD
Dynamic Low
Voltage Input
(note 1, 3)
3.3
0.8
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25
C
-40 to 85
C
-55 to 125
C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time
LE to Q
2.7
15
7.5
14.5
1.0
17.5
1.0
18.5
ns
2.7
50
10.0
18.0
1.0
21.0
1.0
22.0
3.3
(*)
15
6.8
10.3
1.0
12.0
1.0
13.0
3.3
(*)
50
9.3
13.8
1.0
15.5
1.0
16.5
t
PLH
t
PHL
Propagation Delay
Time
D to Q
2.7
15
7.7
15.0
1.0
18.5
1.0
19.5
ns
2.7
50
10.2
18.5
1.0
22.0
1.0
23.0
3.3
(*)
15
5.8
9.7
1.0
11.5
1.0
12.5
3.3
(*)
50
8.5
13.2
1.0
15.0
1.0
16.0
t
PZL
t
PZH
Output Enable
Time
2.7
15
7.7
15.0
1.0
18.5
1.0
19.5
ns
2.7
50
10.2
18.5
1.0
22.0
1.0
23.0
3.3
(*)
15
6.0
9.7
1.0
11.5
1.0
12.5
3.3
(*)
50
8.5
13.2
1.0
15.0
1.0
16.0
t
PLZ
t
PHZ
Output Disable
Time
2.7
50
9.8
18.0
1.0
21.0
1.0
22.0
ns
3.3
(*)
50
8.2
12.8
1.0
14.5
1.0
15.5
t
W
LE pulse Width,
HIGH
2.7
50
6.5
7.5
7.5
ns
3.3
(*)
50
5.0
5.0
5.0
t
S
Setup Time D to LE
HIGH or LOW
2.7
50
6.0
6.0
6.0
ns
3.3
(*)
50
4.0
4.0
4.0
t
h
Hold Time D to LE
HIGH or LOW
2.7
50
1.0
1.0
1.0
ns
3.3
(*)
50
1.0
1.0
1.0
t
OSLH
t
OSHL
Output to Output
Skew Time (note
1,2)
2.7
50
0.5
1.0
1.5
1.5
ns
3.3
(*)
50
0.5
1.0
1.5
1.5
74LVX373
5/10
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per circuit)
TEST CIRCUIT
C
L
=15/50pF or equivalent (includes jig and probe capacitance)
R
L
= R1 = 1K
or equivalent
R
T
= Z
OUT
of pulse generator (typically 50
)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25
C
-40 to 85
C
-55 to 125
C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
3.3
5
10
10
pF
C
OUT
Output
Capacitance
3.3
10
pF
C
PD
Power Dissipation
Capacitance
(note 1)
3.3
f
IN
= 10MHz
40
pF
TEST
SWIT CH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
V
CC
t
PZH
, t
PHZ
GND
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