1/14
August 2004
s
HIGH SPEED:
t
PD
= 5.5ns (TYP.) at V
CC
= 3.3V
s
5V TOLERANT INPUTS
s
INPUT VOLTAGE LEVEL:
V
IL
=0.8V, V
IH
=2V at V
CC
=3V
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
=25C
s
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 594
s
IMPROVED LATCH-UP IMMUNITY
s
POWER DOWN PROTECTION ON INPUTS
DESCRIPTION
The 74LVX594 is a low voltage CMOS 8 BIT
SHIFT REGISTER WITH OUTPUT REGISTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology. It is
ideal for low power, battery operated and low
noise 3.3V applications.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Separate clocks and direct overriding
clear (SCLR, RCLR) are provided for both the shift
register and the storage register. A serial (QH')
output is provided for cascading purposes.
Both
the shift register and storage register use
positive-edge triggered clocks. If the clocks are
connected together, the shift register state will
always be one clock pulse ahead of the storage
register.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V system. It combines
high speed performance with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX594
LOW VOLTAGE CMOS 8 BIT SHIFT REGISTER
WITH OUTPUT REGISTER (5V TOLERANT INPUTS)
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
74LVX594MTR
TSSOP
74LVX594TTR
TSSOP
SOP
Rev. 5
74LVX594
2/14
Figure 2: Input Equivalent Circuit
Table 2: Pin Description
Table 3: Truth Table
X : Don't Care
PIN N
SYMBOL
NAME AND FUNCTION
1, 2, 3, 4, 5,
6, 7, 15
QA to QH
Data Outputs
9
QH'
Serial Data Output
10
SCLR
Shift Register Clear Input
11
SCK
Shift Register Clock Input
13
RCLR
Storage Register Clear
Input
14
SI
Serial Data Input
12
RCK
Storage Register Clock
Input
8
GND
Ground (0V)
16
V
CC
Positive Supply Voltage
INPUTS
OUTPUTS
SI
SCK
SCLR
RCK
RCLR
X
X
L
X
X
SHIFT REGISTER IS CLEAR
L
H
X
X
FIRST STAGE OF SHIFT REGISTER GOES LOW
OTHER STAGES STORE THE DATA OF PREVI-
OUS STAGE, RESPECTIVELY
H
H
X
X
FIRST STAGE OF SHIFT REGISTER GOES HIGH
OTHER STAGES STORE THE DATA OF PREVI-
OUS STAGE, RESPECTIVELY
L
H
X
X
SHIFT REGISTER STATE IS NOT CHANGED
X
X
X
X
L
STORAGE REGISTER IS CLEARED
X
X
X
H
SHIFT REGISTER DATA IS STORED IN THE
STORAGE REGISTER
X
X
X
H
STORAGE REGISTER STATE IS NOT CHANGED
74LVX594
3/14
Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
74LVX594
4/14
Figure 4: Timing Chart
Table 4: Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
74LVX594
5/14
Table 5: Recommended Operating Conditions
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2.0V
Table 6: DC Specifications
Table 7: Dynamic Switching Characteristics
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage (note 1)
2 to 3.6
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time (note 2) (V
CC
= 3.3V)
0 to 100
ns/V
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
3.0
2.0
2.0
2.0
3.6
2.4
2.4
2.4
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
V
3.0
0.8
0.8
0.8
3.6
0.8
0.8
0.8
V
OH
High Level Output
Voltage
2.0
I
O
=-50
A
1.9
2.0
1.9
1.9
V
3.0
I
O
=-50
A
2.9
3.0
2.9
2.9
3.0
I
O
=-4 mA
2.58
2.48
2.4
V
OL
Low Level Output
Voltage
2.0
I
O
=50
A
0.0
0.1
0.1
0.1
V
3.0
I
O
=50
A
0.0
0.1
0.1
0.1
3.0
I
O
=4 mA
0.36
0.44
0.55
I
I
Input Leakage
Current
3.6
V
I
= 5V or GND
0.1
1
1
A
I
off
Power Off Leakage
Current
0
V
I
= 0 to 5V
0.1
5
5
A
I
CC
Quiescent Supply
Current
3.6
V
I
= V
CC
or GND
4
40
40
A
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
OLP
Dynamic Low Voltage
Quiet Output (note 1, 2)
3.3
C
L
= 50 pF
0.3
0.5
V
V
OLV
-0.5
-0.3
V
IHD
Dynamic High Voltage
Input (note 1, 3)
3.3
2
V
ILD
Dynamic Low Voltage
Input (note 1, 3)
3.3
0.8
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