1/11
July 2001
s
HIGH SPEED :
f
MAX
= 145MHz (TYP.) at V
CC
= 3.3V
s
5V TOLERANT INPUTS
s
INPUT VOLTAGE LEVEL :
V
IL
=0.8V, V
IH
=2V AT V
CC
=3V
s
LOW POWER DISSIPATION:
I
CC
= 2
A (MAX.) at T
A
=25C
s
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
s
IMPROVED LATCH-UP IMMUNITY
s
POWER DOWN PROTECTION ON INPUTS
DESCRIPTION
The 74LVX74 is a low voltage CMOS DUAL
D-TYPE FLIP-FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of the
clock pulse. CLR and PR are independent of the
clock and accomplished by a low setting on the
appropriate input.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption. All inputs
and outputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
74LVX74
LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP
WITH PRESET AND CLEAR (5V TOLERANT INPUTS)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
74LVX74M
74LVX74MTR
TSSOP
74LVX74TTR
TSSOP
SOP
74LVX74
2/11
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
PIN No
SYMBOL
NAME AND FUNCTION
1, 13
1CLR, 2CLR
Asynchronous Reset -
Direct Input
2, 12
1D, 2D
Data Inputs
3, 11
1CK, 2CK
Clock Input
(LOW to HIGH, Edge
Triggered)
4, 10
1PR, 2PR
Asynchronous Set - Direct
Input
5, 9
1Q, 2Q
True Flip-Flop Outputs
6, 8
1Q, 2Q
Complement Flip-Flop
Outputs
7
GND
Ground (0V)
14
V
CC
Positive Supply Voltage
INPUTS
OUTPUTS
FUNCTION
CLR
PR
D
CK
Q
Q
L
H
X
X
L
H
CLEAR
H
L
X
X
H
L
PRESET
L
L
X
X
H
H
H
H
L
L
H
H
H
H
H
L
H
H
X
Q
n
Q
n
NO CHANGE
74LVX74
3/11
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2.0V
DC SPECIFICATIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage (note 1)
2 to 3.6
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time (note 2) (V
CC
= 3.3V)
0 to 100
ns/V
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
3.0
2.0
2.0
2.0
3.6
2.4
2.4
2.4
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
V
3.0
0.8
0.8
0.8
3.6
0.8
0.8
0.8
V
OH
High Level Output
Voltage
2.0
I
O
=-50
A
1.9
2.0
1.9
1.9
V
3.0
I
O
=-50
A
2.9
3.0
2.9
2.9
3.0
I
O
=-4 mA
2.58
2.48
2.4
V
OL
Low Level Output
Voltage
2.0
I
O
=50
A
0.0
0.1
0.1
0.1
V
3.0
I
O
=50
A
0.0
0.1
0.1
0.1
3.0
I
O
=4 mA
0.36
0.44
0.55
I
I
Input Leakage
Current
3.6
V
I
= 5V or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
3.6
V
I
= V
CC
or GND
2
20
20
A
74LVX74
4/11
DYNAMIC SWITCHING CHARACTERISTICS
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
3.3
C
L
= 50 pF
0.3
0.5
V
V
OLV
-0.5
-0.3
V
IHD
Dynamic High
Voltage Input (note
1, 3)
3.3
2
V
ILD
Dynamic Low
Voltage Input (note
1, 3)
3.3
0.8
74LVX74
5/11
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
0.3V
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/2 (per circuit)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time CK to
Q or Q
2.7
15
7.3
15.0
1.0
18.5
1.0
18.5
ns
2.7
50
9.8
18.5
1.0
22.0
1.0
22.0
3.3
(*)
15
5.7
9.7
1.0
11.5
1.0
11.5
3.3
(*)
50
8.2
13.2
1.0
15.0
1.0
15.0
t
PLH
t
PHL
Propagation Delay
Time
PR or CLR to
Q or Q
2.7
15
8.4
15.6
1.0
18.5
1.0
18.5
ns
2.7
50
10.9
19.1
1.0
22.0
1.0
22.0
3.3
(*)
15
6.6
10.1
1.0
12.0
1.0
12.0
3.3
(*)
50
9.1
13.6
1.0
15.5
1.0
15.5
t
w
Minimum Pulse
Width HIGH or
LOW, CK
2.7
50
8.5
10.0
10.0
ns
3.3
(*)
50
6.0
7.0
7.0
t
w(L)
Minimum Pulse
Width LOW
PR or CLR
2.7
50
8.5
10.0
10.0
ns
3.3
(*)
50
6.0
7.0
7.0
t
s
Minimum Setup
Time D to CK
HIGH or LOW
2.7
50
8.0
9.5
9.5
ns
3.3
(*)
50
5.5
6.5
6.5
t
h
Minimum Hold
Time D to CK
HIGH or LOW
2.7
50
0.5
0.5
0.5
ns
3.3
(*)
50
0.5
0.5
0.5
t
REM
Minimum Removal
Time PR or CLR to
CK
2.7
50
6.5
7.5
7.5
ns
3.3
(*)
50
5.0
5.0
5.0
f
MAX
Maximum Clock
Frequency
2.7
15
55
135
50
50
MHz
2.7
50
45
60
40
40
3.3
(*)
15
95
145
80
80
3.3
(*)
50
60
85
50
50
t
OSLH
t
OSHL
Output To Output
Skew Time (note1,
2)
2.7
50
0.5
1.0
1.5
1.5
ns
3.3
(*)
50
0.5
1.0
1.5
1.5
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
3.3
4
10
10
10
pF
C
PD
Power Dissipation
Capacitance
(note 1)
3.3
f
IN
= 10 MHz
25
pF
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