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L6258EP

July 2005

FEATURES

ABLE TO DRIVE BOTH WINDINGS OF A
BIPOLAR STEPPER MOTOR OR TWO DC
MOTORS

OUTPUT CURRENT UP TO 1.3A EACH
WINDING

WIDE VOLTAGE RANGE: 12V TO 40V

FOUR QUADRANT CURRENT CONTROL,
IDEAL FOR MICROSTEPPING AND DC
MOTOR CONTROL

PRECISION PWM CONTROL

NO NEED FOR RECIRCULATION DIODES

TTL/CMOS COMPATIBLE INPUTS

CROSS CONDUCTION PROTECTION

THERMAL SHUTDOW

DESCRIPTION

L6258EP is a dual full bridge for motor control appli-
cations realized in BCD technology, with the capabil-
ity of driving both windings of a bipolar stepper motor
or bidirectionally control two DC motors.
L6258EP and a few external components form a

complete control and drive circuit. It has high efficien-
cy phase shift chopping that allows a very low current
ripple at the lowest current control levels, and makes
this device ideal for steppers as well as for DC mo-
tors.The power stage is a dual DMOS full bridge ca-
pable of sustaining up to 40V, and includes the
diodes for current recirculation.The output current ca-
pability is 1.3A per winding in continuous mode, with
peak start-up current up to 2A. A thermal protection
circuitry disables the outputs if the chip temperature
exceeds the safe limits.

DATASHEET

PWM CONTROLLED - HIGH CURRENT

DMOS UNIVERSAL MOTOR DRIVER

Figure 2. Block Diagram

DAC

CHARGE

PUMP

/2)

VCP1

PH_1

I0_1

I1_1

I2_1

VREF1

TRIANGLE

GENERATOR

TRI_CAP

ERROR

AMP

POWER
BRIDGE

TRI_0

TRI_180

TRI_0

DAC

PH_2

I0_2

I1_2

I2_2

VREF1

ERROR

AMP

POWER
BRIDGE

TRI_0

TRI_180

THERMAL

PROT.

OUT1A

OUT1B

SENSE1A

VBOOT

DISABLE

OUT2A

OUT2B

SENSE2A

EA_IN2

EA_OUT2

GND

EA_IN1

EA_OUT1

VCP2

(5V)

D96IN430D

VR GEN

INPUT

SENSE

AMP

FREF

BOOT

INPUT

SENSE

AMP

I3_1

I3_2

SENSE1B

SENSE2B

Rev. 3

Figure 1. Package

Table 1. Order Codes

Part Number

Package

E-L6258EP

PowerSSO36

PowerSSO36

L6258EP

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Table 2. Absolute Maximum Ratings

(1) This current is intended as not repetitive current for max. 1 second.

Figure 3. Pin Connection (Top view)

Symbol

Parameter

Value

Unit

Supply Voltage

Logic Supply Voltage

ref1

ref2

Reference Voltage

2.5

Output Current (peak)

(1)

Output Current (continuous)

1.3

Logic Input Voltage Range

-0.3 to 7

boot

Bootstrap Supply

boot

- V

Maximum Vgate applicable

Junction Temperature

150

�C

stg

Storage Temperature Range

-55 to 150

�C

PWR_GND

PH_2

EA_IN2

EA_OUT2

DISABLE

EA_OUT1

OUT1A

EA_IN1

PH_1

SENSE1

OUT1B

I3_1

I2_1

I3_2

OUT2B

SENSE2

PWR_GND

D96IN432E

GND

TRI_CAP

I0_1

VREF1

I1_1

VCP1

SIG_GND

OUT2A

VCP2

VBOOT

VREF2

I2_2

I0_2

I1_2

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L6258EP

Table 3. Pins Function

Note: The number in parenthesis shows the relevant Power Bridge of the circuit. Pins 18, 19, 1 and 36 are connected together.

Pin #

Name

Description

1, 36

PWR_GND

Ground connection (1). They also conduct heat from die to printed circuit copper.

2, 17

PH_1, PH_2

These TTL compatible logic inputs set the direction of current flow through the load. A
high level causes current to flow from OUTPUT A to OUTPUT B.

1_1

Logic input of the internal DAC (1). The output voltage of the DAC is a percentage of the
Vref voltage applied according to the thruth table of page 7

0_1

See pin 3

OUT1A

Bridge output connection (1)

DISABLE

Disables the bridges for additional safety during switching. When not connected the
bridges are enabled

TRI_cap

Triangular wave generation circuit capacitor. The value of this capacitor defines the output
switching frequency

(5V)

Supply Voltage Input for logic circuitry

GND

Power Ground connection of the internal charge pump circuit

CP1

Charge pump oscillator output

CP2

Input for external charge pump capacitor

BOOT

Overvoltage input for driving of the upper DMOS

13, 31

Supply voltage input for output stage. They are shorted internally

OUT2A

Bridge output connection (2)

0_2

Logic input of the internal DAC (2). The output voltage of the DAC is a percentage of the
VRef voltage applied according to the truth table of page 7

1_2

See pin 15

18, 19

PWR_GND

Ground connection. They also conduct heat from die to printed circuit copper

20, 35

SENSE2,

SENSE1

Negative input of the transconductance input amplifier (2, 1)

OUT2B

Bridge output connection and positive input of the tranconductance (2)

3_2

See pin 15

2_2

See pin 15

EA_OUT_2

Error amplifier output (2)

EA_IN_2

Negative input of error amplifier (2)

26, 28

REF2

, V

REF1

Reference voltages for the internal DACs, determining the output current value. Output
current also depends on the logic inputs of the DAC and on the sensing resistor value

SIG_GND

Signal ground connection

EA_IN_1

Negative input of error amplifier (1)

EA_OUT_1

Error amplifier output (1)

2_1

See pin 3

3_1

See pin 3

OUT1B

Bridge output connection and positive input of the tranconductance (1)

L6258EP

4/22

Table 4. Electrical Characteristics (V

= 40V; V

= 5V; T

= 25�; unless otherwise specified.)

Note 1: This is true for all the logic inputs except the disable input.
(*) Chopping frequency is twice fosc value.

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Supply Voltage

Logic Supply Voltage

4.75

5.25

BOOT

Storage Voltage

= 12 to 40V

+12

Sense

Max Drop Across Sense Resistor

1.25

S(off)

Power off Reset

Off Threshold

7.2

DD(off)

Power off Reset

Off Threshold

3.3

4.1

S(on)

VS Quiescent Current

Both bridges ON, No Load

S(off)

VS Quiescent Current

Both bridges OFF

VDD Operative Current

SD-H

Shut Down Hysteresis

�C

Thermal shutdown

150

�C

osc

Triangular Oscillator Frequency

(*)

FREF

= 1nF

12.5

18.5

KHz

TRANSISTORS

DSS

Leakage Current

OFF State

500

�A

ds(on)

On Resistance

ON State

0.6

0.75

Flywheel diode Voltage

If =1.0A

1.4

CONTROL LOGIC

in(H)

lnput Voltage

All Inputs

in(L)

Input Voltage

All Inputs

0.8

Input Current (Note 1)

0 < V

< 5V

-150

+10

�A

dis

Disable Pin Input Current

-10

+150

�A

ref1

ref2

Reference Voltage

operating

2.5

ref

Terminal Input Current

ref

= 1.25

-2

�A

FI =

ref

sense

PWM Loop Transfer Ratio

DAC Full Scale Precision

ref

= 2.5V I

= L

1.23

1.34

offset

Current Loop Offset

ref

= 2.5V I

= H

-40

+40

DAC Factor Ratio

Normalized @ Full scale Value

-2

SENSE AMPLIFIER

lnput Common Mode Voltage
Range

-0.7

+0.7

inp

Input Bias

sense1/sense2

-200

�A

ERROR AMPLIFIER

Open Loop Voltage Gain

Output Slew Rate

Open Loop

0.2

�s

GBW

Gain Bandwidth Product

400

kHz

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L6258EP

FUNCTIONAL DESCRIPTION

The circuit is intended to drive both windings of a bipolar stepper motor or two DC motors.

The current control is generated through a switch mode regulation.

With this system the direction and the amplitude of the load current are depending on the relation of phase and
duty cycle between the two outputs of the current control loop.

The L6258EP power stage is composed by power DMOS in bridge configuration as it is shown in figure 4, where
the bridge outputs OUT_A and OUT_B are driven to V

with an high level at the inputs IN_A and IN_B while are

driven to ground with a low level at the same inputs .

The zero current condition is obtained by driving the two half bridge using signals IN_A and IN_B with the same
phase and 50% of duty cycle.

In this case the outputs of the two half bridges are continuously switched between power supply (V

) and

ground, but keeping the differential voltage across the load equal to zero.

In figure 4A is shown the timing diagram of the two outputs and the load current for this working condition.

Following we consider positive the current flowing into the load with a direction from OUT_A to OUT_B, while
we consider negative the current flowing into load with a direction from OUT_B to OUT_A.

Now just increasing the duty cycle of the IN_A signal and decreasing the duty cycle of IN_B signal we drive pos-
itive current into the load.

In this way the two outputs are not in phase, and the current can flow into the load trough the diagonal bridge
formed by T1 and T4 when the output OUT_A is driven to V

and the output OUT_B is driven to ground, while

there will be a current recirculation into the higher side of the bridge, through T1 and T2, when both the outputs
are at Vs and a current recirculation into the lower side of the bridge, through T3 and T4, when both the outputs
are connected to ground.

Since the voltage applied to the load for recirculation is low, the resulting current discharge time constant is high-
er than the current charging time constant during the period in which the current flows into the load through the
diagonal bridge formed by T1 and T4. In this way the load current will be positive with an average amplitude
depending on the difference in duty cycle of the two driving signals.

In figure 4B is shown the timing diagram in the case of positive load current

On the contrary, if we want to drive negative current into the load is necessary to decrease the duty cycle of the
IN_A signal and increase the duty cycle of the IN_B signal. In this way we obtain a phase shift between the two
outputs such to have current flowing into the diagonal bridge formed by T2 and T3 when the output OUT_A is
driven to ground and output OUT_B is driven to Vs, while we will have the same current recirculation conditions
of the previous case when both the outputs are driven to Vs or to ground.

So, in this case the load current will be negative with an average amplitude always depending by the difference
in duty cycle of the two driving signals.

In figure 4C is shown the timing diagram in the case of negative load current .

Figure 5 shows the device block diagram of the complete current control loop.

3.1 Reference Voltage

The voltage applied to VREF pin is the reference for the internal DAC and, together with the sense resistor val-
ue, defines the maximum current into the motor winding according to the following relation:

where R

= sense resistor value

MAX

0.5 V

REF

---------------------------

-----

REF

--------------

Электронный компонент: E-L6258EP

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