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ESDAxxL
Marchr 2000 - Ed: 4A
DUAL TRANSIL ARRAY
FOR ESD PROTECTION
SOT23
Where transient overvoltage protection in ESD
sensitive equipment is required, such as :
- COMPUTERS
- PRINTERS
- COMMUNICATION SYSTEMS
It is particulary recommended for the RS232 I/O
port protection where the line interface withstands
only with 2kV ESD surges.
APPLICATIONS
Application Specific Discretes
A.S.D.
FUNCTIONAL DIAGRAM
n
2 UNIDIRECTIONAL TRANSIL FUNCTIONS.
n
LOW LEAKAGE CURRENT : I
R
max. < 20
A at
V
BR
.
n
300 W PEAK PULSE POWER (8/20
s)
FEATURES
DESCRIPTION
The ESDAxxL is a dual monolithic voltage
suppressor designed to protect components which
are connected to data and transmission lines
against ESD.
It clamps the voltage just above the logic level
supply for positive transients, and to a diode drop
below ground for negative transients.
It can also work as bidirectionnal suppressor by
connecting only pin1 and 2.
BENEFITS
High ESD protection level : up to 25 kV.
High integration.
Suitable for high density boards.
IEC61000-4-2 level 4
MIL STD 883C-Method 3015-6 : class 3.
(human body model)
COMPLIES WITH THE FOLLOWING STANDARDS :
ESDAxxL
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Symbol
Parameter
V
RM
Stand-off voltage
V
BR
Breakdown voltage
V
CL
Clamping voltage
I
RM
Leakage current
I
PP
Peak pulse current
T
Voltage temperature coefficient
C
Capacitance
Rd
Dynamic resistance
V
F
Forward voltage drop
ELECTRICAL CHARACTERISTICS (T
amb
= 25C)
I
IF
V F
VBR
VRM
I PP
I RM
V
1
Rd
Slope:
Symbol
Parameter
Value
Unit
V
PP
Electrostatic discharge
MIL STD 883C - Method 3015-6
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
25
16
9
kV
P
PP
Peak pulse power (8/20
s)
300
W
T
stg
T
j
Storage temperature range
Maximum junction temperature
- 55 to + 150
150
C
C
T
L
Maximum lead temperature for soldering during 10s
260
C
T
op
Operating temperature range
- 40 to + 125
C
note 1: Evolution of functional parameters is given by curves.
ABSOLUTE MAXIMUM RATINGS (T
amb
= 25C)
Types
V
BR
@
I
R
I
RM
@
V
RM
Rd
T
C
V
F
@
I
F
min.
max.
max.
typ.
max.
typ.
max.
note 1
note 2
0V bias
V
V
mA
A
V
m
10
-4
/
C
pF
V
mA
ESDA5V3L
5.3
5.9
1
2
3
280
5
220
1.25
200
ESDA6V1L
6.1
7.2
1
20
5.25
350
6
140
1.25
200
ESDA14V2L
14.2
15.8
1
5
12
650
10
90
1.25
200
ESDA25L
25
30
1
1
24
1000
10
50
1.2
10
note 1 : Square pulse Ipp = 15A, tp=2.5
s.
note 2 :
VBR =
T* (Tamb -25C) * VBR (25C)
ESDAxxL
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The ESDA family has been designed to clamp fast
spikes like ESD. Generally the PCB designers
need to calculate easily the clamping voltage V
CL
.
This is why we give the dynamic resistance in
addition to the classical parameters. The voltage
across the protection cell can be calculated with
the following formula:
V
CL
= V
BR
+ Rd I
PP
Where Ipp is the peak current through the ESDA cell.
DYNAMIC RESISTANCE MEASUREMENT
The short duration of the ESD has led us to prefer
a more adapted test wave, as below defined, to the
classical 8/20
s and 10/1000
s surges.
2.5
s duration measurement wave.
As the value of the dynamic resistance remains
stable for a surge duration lower than 20
s, the
2.5
s rectangular surge is well adapted. In
addition both rise and fall times are optimized to
avoid any parasitic phenomenon during the
measurement of Rd.
CALCULATION OF THE CLAMPING VOLTAGE
USE OF THE DYNAMIC RESISTANCE
2s
tp = 2.5s
t
I
Ipp
ESDAxxL
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25
50
75
100
125
1
10
100
200
Tj(C)
IR[Tj] / IR[Tj=25C]
ESDA6V1L
&
ESDA14V2L
ESDA5V3L
ESDA25L
Fig. 5: Relative variation of leakage current versus
junction temperature (typical values).
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.01
0.10
1.00
5.00
VFM(V)
IFM(A)
Tj=25C
ESDA5V3L
ESDA6V1L
ESDA14V2L
ESDA25L
Fig. 6: Peak forward voltage drop versus peak for-
ward current (typical values).
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
0.1
1.0
10.0
50.0
Vcl(V)
Ipp(A)
tp=2.5s
ESDA6V1L
ESDA14V2L
ESDA5V3L
ESDA25L
Fig. 3: Clamping voltage versus peak pulse cur-
rent (Tj initial = 25 C).
Rectangular waveform tp = 2.5
s.
1
2
5
10
20
50
10
20
50
100
200
VR(V)
C(pF)
F=1MHz
Vosc=30mV
ESDA6V1L
ESDA14V2L
ESDA5V3L
ESDA25L
Fig. 4: Capacitance versus reverse applied volt-
age (typical values).
0
25
50
75
100
125
150
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
Tj initial(C)
Ppp[Tj initial]/Ppp[Tj initial=25C]
Fig. 1: Peak power dissipation versus initial junc-
tion temperature.
1
10
100
10
100
1000
3000
tp(s)
Ppp(W)
Fig.
2: Peak pulse power versus exponential
pulse duration (Tj initial = 25 C).
ESDAxxL
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ESD
sensitive
device
GND
2 * ESDAXXL
I/O
I/O
I/O
I/O
1. ESD protection by the ESDAxxL
Electrostatic discharge (ESD) is a major cause of
failure in electronic systems.
Transient Voltage Suppressors (TVS) are an ideal
choice for ESD protection. They are capable of
clamping the incoming transient to a low enough
level
such
that
damage
to
the
protected
semiconductor is prevented.
Surface mount TVS arrays offer the best choice for
minimal lead inductance.
They serve as parallel protection elements,
connected between the signal line to ground. As
the transient rises above the operating voltage of
the device, the TVS array becomes a low
impedance path diverting the transient current to
ground.
The ESDAxxL array is the ideal board level
protection
of
ESD
sensitive
semiconductor
components.
The tiny SOT23 package allows design flexibility in
the design of high density boards where the space
saving is at a premium. This enables to shorten the
routing and contributes to hardening againt ESD.
2. Circuit Board Layout
Circuit board layout is a critical design step in the
suppression of ESD induced transients. The
following guidelines are recommended :
n
The ESDAxxL should be placed as close as pos-
sible to the input terminals or connectors.
n
The path length between the ESD suppressor
and the protected line should be minimized
n
All conductive loops, including power and
ground loops should be minimized
n
The ESD transient return path to ground should
be kept as short as possible.
n
Ground planes should be used whenever possi-
ble.
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