ESDA6V1W5
September 1999 - Ed: 1A
QUAL TRANSIL
TM
ARRAY
FOR ESD PROTECTION
SOT323-5L
Where transient overvoltage protection in ESD
sensitive equipment is required, such as :
Computers
Printers
Communication systems
GSM handsets and accessories
Other telephone sets
Set top boxes
MAIN APPLICATIONS
Application Specific Discretes
A.S.D.
TM
FUNCTIONAL DIAGRAM
1
2
3
4
5
4 unidirectional TRANSIL
TM
functions.
Breakdown voltage : V
BR
= 6.1 V min.
Low leakage current : < 1
A.
Very low PCB space consuming : 4.2 mm
2
typically.
FEATURES
DESCRIPTION
The ESDA6V1W5 is a 4-bit wide monolithic
suppressor which is designed to protect component
connected to data and transmission lines against
ESD.
It clamps the voltage just above the logic level
supply for positive transients, and to a diode drop
below ground for negative transients.
BENEFITS
High ESD protection level : up to 25 kV.
High integration.
Suitable for high density boards.
IEC 1000-4-2 level 4
MIL STD 883C-Method 3015-6 : class 3.
(human body model)
COMPLIES WITH THE FOLLOWING STANDARDS :
ESD RESPONSE TO IEC1000-4-2
(air discharge 16 kV, positive surge)
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Symbol
Parameter
V
RM
Stand-off voltage
V
BR
Breakdown voltage
V
CL
Clamping voltage
I
RM
Leakage current
I
PP
Peak pulse current
T
Voltage temperature coefficient
C
Capacitance per line
Rd
Dynamic resistance
V
F
Forward voltage drop
ELECTRICAL CHARACTERISTICS (T
amb
= 25C)
V
I
V
RM
PP
I
RM
I
V
BR
R
I
V
CL
slope : 1 / R
d
Symbol
Parameter
Test conditions
Value
Unit
V
PP
ESD discharge
MIL STD 883C - Method 3015-6
IEC1000-4-2, air discharge
IEC1000-4-2, contact discharge
25
16
9
kV
P
PP
Peak pulse power (8/20
s)
150
W
T
op
Operating temperature range
- 40 to + 85
C
T
j
Junction temperature
150
C
T
stg
Storage temperature range
- 55 to + 150
C
T
L
Lead solder temperature (10 secondes duration)
260
C
ABSOLUTE MAXIMUM RATINGS (T
amb
= 25C)
Types
V
BR
@
I
R
I
RM
@ V
RM
Rd
T
C
V
F
@ I
F
min.
max.
max.
typ.
max.
typ.
max.
note 1
note 2
0V bias
V
V
mA
A
V
m
10
-4
/
C
pF
V
mA
ESDA6V1W5
6.1
7.2
1
1
3
350
6
90
1.25
200
note 1 : Square pulse Ipp = 15A, tp=2.5
s.
note 2 :
VBR =
T* (Tamb -25C) * VBR (25C)
ESDA6V1W5
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The ESDA family has been designed to clamp fast
spikes like ESD. Generally the PCB designers
need to calculate easily the clamping voltage V
CL
.
This is why we give the dynamic resistance in
addition to the classical parameters. The voltage
across the protection cell can be calculated with
the following formula:
V
CL
= V
BR
+ Rd I
PP
Where Ipp is the peak current through the ESDA cell.
DYNAMIC RESISTANCE MEASUREMENT
The short duration of the ESD has led us to prefer
a more adapted test wave, as below defined, to the
classical 8/20
s and 10/1000
s surges.
2.5
s duration measurement wave.
As the value of the dynamic resistance remains
stable for a surge duration lower than 20
s, the
2.5
s rectangular surge is well adapted. In addition
both rise and fall times are optimized to avoid any
parasitic phenomenon during the measurement of
Rd.
CALCULATION OF THE CLAMPING VOLTAGE
USE OF THE DYNAMIC RESISTANCE
2s
tp = 2.5s
t
I
Ipp
ESDA6V1W5
3/7
25
50
75
100
125
150
1
2
3
4
5
IR[Tj] / IR[Tj=25C]
Tj(C)
Fig. 5 : Relative variation of leakage current
versus junction temperature (typical values).
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1E-3
1E-2
1E-1
1E+0
IFM(A)
Tj=25C
VFM(V)
Fig. 6 : Peak forward voltage drop versus peak
forward current (typical values).
0
5
10
15
20
25
30
0.1
1.0
10.0
50.0
Ipp(A)
tp=2.5s
Vcl(V)
Fig. 3 : Clamping voltage versus peak pulse
current (Tj initial = 25 C).
Rectangular waveform tp = 2.5
s.
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10
20
30
40
50
60
70
80
90
C(pF)
F=1MHz
Vosc=30mV
VR(V)
Fig. 4 : Capacitance versus reverse applied
voltage (typical values).
0
25
50
75
100
125
150
175
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
Ppp[Tj initial]/Ppp[Tj initial=25C]
Tj initial(C)
Fig. 1 : Peak power dissipation versus initial
junction temperature
1
10
100
10
100
1000
Ppp(W)
tp(s)
Fig. 2 : Peak pulse power versus exponential
pulse duration (Tj initial = 25 C)
ESDA6V1W5
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With the focus of lowering the operation levels, the problem of malfunction caused by the environment is
critical. Electrostatic discharge (ESD) is a major cause of failure in electronic system.
Transient Voltage Suppressors are an ideal choice for ESD protection and have proven capable in
suppressing ESD events. They are capable of clamping the incoming transient to a low enough level such
that damage to the protected semiconductor is prevented.
Surface mount TVS arrays offer the best choice for minimal lead inductance.
They serve as parallel protection elements, connected between the signal line to ground. As the transient
rises above the operating voltage of the device, the TVS array becomes a low impedance path diverting the
transient current to ground.
1. ESD protection by the ESDA6V1W5
Circuit board layout is a critical design step in the suppression of ESD induced transients. The following
guidelines are recommended :
The ESDA6V1W5 should be placed as near as possible to the input terminals or connectors.
Minimise the path length between the ESD suppressor and the protected device
Minimise all conductive loops, including power and ground loops
The ESD transient return path to ground should be kept as short as possible.
Use ground planes whenever possible.
2. Circuit Board Layout
The ESDA6V1W5 array is the ideal product for use as board level protection of ESD sensitive
semiconductor components.
The tiny SOT323-5L package makes the ESDA6V1W5 device some of the smallest ESD protection
devices available. It also allows design flexibility in the design of "crowded" boards where the space saving
is at a premium. This enables to shorten the routing and can contribute to improved ESD performance.
Keyboard
terminal
printer
etc
I / O
FUNCTIONAL
DECODER
A
B
C
D
ESDA6V1W5
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