SERIAL INTERFACE CODEC/FILTER

ETC5054
ETC5057

COMPLETE CODEC AND FILTERING SYS-
TEM (DEVICE) INCLUDING:
Transmit high-pass and low-pass filtering.
Receive low-pass filter with sin x/x correction.
Active RC noise filters

-law or A-law compatible COder and DECoder.

Internal precision voltage reference.
Serial I/O interface.
Internal auto-zero circuitry.
A-LAW 16 PINS (ETC5057FN, 20 PINS)

-LAW WITHOUT SIGNALING, 16 PINS

(ETC5054FN, 20 PINS)
MEETS OR EXCEEDS ALL D3/D4 AND
CCITT SPECIFICATIONS

5V OPERATION

LOW OPERATING POWER - TYPICALLY 60
mW
POWER-DOWN STANDBY MODE - TYPI-
CALLY 3 mW
AUTOMATIC POWER-DOWN
TTL OR CMOS COMPATIBLE DIGITAL IN-
TERFACES
MAXIMIZES LINE INTERFACE CARD CIR-
CUIT DENSITY
0 to 70

C OPERATION

DESCRIPTION
The ETC5057/ETC5054 family consists of A-law
and

law monolithic PCM CODEC/filters utilizing

the A/D and D/A conversion architecture shown in
the block diagram below, and a serial PCM inter-
face. The devices are fabricated using double-
poly CMOS process. The encode portion of each
device consists of an input gain adjust amplifier,
an active RC pre-filter which eliminates very high
frequency noise prior to entering a switched-ca-
pacitor band-pass filter that rejects signals below
200 Hz and above 3400 Hz. Also included are
auto-zero circuitry and a companding coder which
samples the filtered signal and encodes it in the
companded A-law or

law PCM format. The de-

code portion of each device consists of an ex-
panding decoder, which reconstructs the analog
signal from the companded A-law or

law code,

a low-pass filter which corrects for the sin x/x re-
sponse of the decoder output and rejects signals
above 3400 Hz and is followed by a single-ended
power amplifier capable of driving low impedance
loads. The devices require 1.536 MHz, 1.544

MHz, or 2.048 MHz transmit and receive master
clocks, which may be asynchronous, transmit and
receive bit clocks which may vary from 64 kHz to
2.048 MHz, and transmit and receive frame sync
pulses. The timing of the frame sync pulses and
PCM data is compatible with both industry stand-
ard formats.

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

March 2000

DIP16 (Plastic)

ORDERING NUMBERS:

ETC5057N
ETC5054N

SO16 (Wide)

ORDERING NUMBERS:

ETC5057D
ETC5054D

PLCC20

ORDERING NUMBERS:

ETC5057FN
ETC5054FN

1/18

PIN DESCRIPTION

Name

Pin

Type

DIP
and

PLCC

(**)

Function

Description

Negative

Power Supply

= 5 V

5 %.

GNDA

GND

Analog Ground

All signals are referenced to this pin.

Receive Filter

Output

Analog Output of the Receive Filter

Positive Power

Supply

= + 5 V

5 %.

Receive Frame

Sync Pulse

Enables BCLK

to shift PCM data into D

. FS

is an

8kHz pulse train. See figures 1, 2 and 3 for timing
details.

Receive Data

Input

PCM data is shifted into D

following the FS

leading

edge.

BCLK

/CLKSEL

Shift-in Clock

Shifts data into D

after the FS

leading edge. May

vary from 64 kHz to 2.048 MHz. Alternatively, may be
a logic input which selects either 1.536 MHz/1.544
MHz or 2.048 MHz for master clock in synchronous
mode and BCLK

is used for both transmit and receive

directions (see table 1). This input has an internal pull-
up.

MCLK

/PDN

Receive Master Clock

Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK

, but should be

synchronous with MCLK

for best performance. When

MCLK

is connected continuously low, MCLK

selected for all internal timing. When MCLK

connected continuously high, the device is powered
down.

MCLK

Transmit Master Clock

Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK

BCLK

Shift-out Clock

Shifts out the PCM data on DX. May vary from 64 kHz
to 2.048 MHz, but must be synchronous with MCLK

Transmit

Data Output

The TRI-STATE

PCM data output which is enabled

by FS

Transmit Frame

Sync Pulse

Enables BCLK

to shift out the PCM data on D

. FS

an 8 kHz pulse train. See figures 1, 2 and 3 for timing
details.

Transmit Time Slot

Open drain output which pulses low during the encoder
time slot. Recommended to be grounded if not used.

Gain Set

Analog output of the transmit input amplifier. Used to
set gain externally.

Inverting Amplifier

Input

Inverting Input of the Transmit Input Amplifier.

Non-inverting Amplifier

Input

Non-inverting Input of the Transmit Input Amplifier.

(*) I: Input, O: Output, S: Power Supply
(**) Pins 4,10,11 and 13 are not connected
TRI-STATE® is a trademark of National Semiconductor Corp.

ETC5054 - ETC5057

3/18

FUNCTIONAL DESCRIPTION
POWER-UP
When power is first applied, power-on reset cir-
cuitry initializes the device and places it into
the power-down mode. All non-essential circuits
are deactivated and the D

and VF

O outputs are

put in high impedance states. To power-up the
device, a logical low level or clock must be ap-
plied to the MCLK

/PDN pin and FS

and/or FS

pulses must be present. Thus, 2 power-down
control modes are available. The first is to pull the
MCLK

/PDN pin high ; the alternative is to hold

both FS

and FS

inputs continuously low. The

device will power-down approximately 2 ms after
the last FS

or FS

pulse. Power-up will occur on

the first FS

or FS

pulse. The TRI-STATE PCM

data output, D

, will remain in the high impedance

state until the second FS

pulse.

SYNCHRONOUS OPERATION
For synchronous operation, the same master
clock and bit clock should be used for both the
transmit and receive directions. In this mode, a
clock must be applied to MCLK

and the

MCLK

/PDN pin can be used as a power-down

control. A low level on MCLK

/PDN powers up

the device and a high level powers down the de-
vice. In either case, MCLK

will be selected as

the master clock for both the transmit and receive
circuits. A bit clock must also be applied to BCLK

and the BCLK

/CKSEL can be used to select the

proper internal divider for a master clock of 1.536
MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz
operation, the device automatically compensates
for the 193rd clock pulse each frame. With a fixed
level on the BCLK

/CLKSEL pin, BCLK

will be

selected as the bit clock for both the transmit and
receive directions. Table 1 indicates the frequen-
cies of operation which can be selected, depend-
ing on the state of BCLK

/CLKSEL. In this syn-

chronous mode, the bit clock, BCLK

, may be

from 64 kHz to 2.048 MHz, but must be synchro-
nous with MCLK

Each FS

pulse begins the encoding cycle and

the PCM data from the previous encode cycle is
shifted out of the enabled D

output on the posi-

tive edge of BCLK

. After 8 bit clock periods, the

TRI-STATE D

output is returned to a high im-

pedance state. With and FS

pulse, PCM data is

latched via the D

input on the negative edge of

BCLK

(or BCLK

if running). FS

and FS

must

be synchronous with MCLK

X/R

ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit
and receive clocks may be applied, MCLK

and

MCLK

must be 2.048 MHz for the ETC5057, or

1.536 MHz, 1.544 MHz for the ETC5054, and
need not be synchronous. For best transmission
performance, however, MCLK

should be syn-

chronous with MCLK

, which is easily achieved

by applying only static logic levels to the
MCLK

/PDN pin. This will automatically connect

MCLK

to all internal MCLK

functions (see pin

description). For 1.544 MHz operation, the device
automatically compensates for the 193rd clock
pulse each frame. FS

starts each encoding cycle

and must be synchronous with MCLK

and

BCLK

. FS

starts each decoding cycle and must

be synchronous with BCLK

. BCLK

must be a

clock, the logic levels shown in table 1 are not
valid in asynchronous mode. BCLK

and BCLK

may operate from 64 kHz to 2.048 MHz.

SHORT FRAME SYNC OPERATION
The device can utilize either a short frame sync
pulse or a long frame sync pulse. Upon power in-
itialization, the device assumes a short frame
mode. In this mode, both frame sync pulses, FS

and FS

, must be one bit clock period long, with

timing relationships specified in figure 2. With FS

high during a falling edge of BCLK

the next ris-

ing edge of BCLK

enables the D

TRI-STATE

output buffer, which will output the sign bit. The
following seven rising edges clock out the remain-
ing seven bits, and the next falling edge disables
the D

output. With FS

high during a falling edge

of BCLK

(BCLK

in synchronous mode), the

next falling edge of BCLK

latches in the sign bit.

The following seven falling edges latch in the
seven remaining bits. Both devices may utilize the
short frame sync pulse in synchronous or asyn-
chronous operating mode.

LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync
pulses, FS

and FS

, must be three or more bit

clock periods long, with timing relationships speci-
fied in figure 3. Based on the transmit frame sync,
FS

, the device will sense whether short or long

frame sync pulses are being used. For 64 kHz op-
eration, the frame sync pulse must be kept low for
a minimum of 160 ns (see fig. 1). The D

TRI-

STATE output buffer is enabled with the rising
edge of FS

or the rising edge of BCLK

, which-

ever comes later, and the first bit clocked out is
the sign bit. The following seven BCLK

rising

Table 1:

Selection

Master

Clock

Frequencies.

BCLK

/CLKSEL

Master Clock Frequency

Selected

ETC5057

ETC5054

Clocked

1 (or open circuit)

2.048 MHz

1.536 MHz or
1.544 MHz

2.048 MHz

1.536 MHz or

1.544 MHz
2.048 MHz

1.536 MHz or

1.544 MHz

ETC5054 - ETC5057

4/18

edges clock out the remaining seven bits. The D

output is disabled by the falling BCLK

edge fol-

lowing the eighth rising edge, or by FS

going

low, which-ever comes later. A rising edge on the
receive frame sync pulse, FS

, will cause the

PCM data at D

to be latched in on the next eight

falling edges of BCLK

(BCLK

in synchronous

mode). Both devices may utilize the long frame
sync pulse in synchronous or asynchronous
mode.

TRANSMIT SECTION
The transmit section input is an operational ampli-
fier with provision for gain adjustment using two
external resistors, see figure 6. The low noise and
wide bandwidth allow gains in excess of 20 dB
across the audio passband to be realized. The op
amp drives a unitygain filter consisting of RD ac-
tive pre-filter, followed by an eighth order
switched-capacitor bandpass filter clocked at 256
kHz. The output of this filter directly drives the en-
coder sample-and-hold circuit. The A/D is of com-
panding type according to A-law (ETC5057) or

law (ETC5054) coding conventions. A precision
voltage reference is trimmed in manufacturing to
provide an input overload (t

MAX

) of nominally 2.5V

peak (see table of transmission characteristics).
The FS

frame sync pulse controls the sampling

of the filter output, and then the successive-ap-

proximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out
through D

at the next FS

pulse. The total en-

coding delay will be approximately 165

s (due to

the transmit filter) plus 125

s (due to encoding

delay), which totals 290

s. Any offset vol-tage

due to the filters or comparator is cancelled by
sign bit integration.

RECEIVE SECTION
The receive section consists of an expanding
DAC which drives a fifth order switched-capacitor
low pass filter clocked at 256 kHz. The decoder is
A-law (ETC5057) or

law (ETC5054) and the

5th order low pass filter corrects for the sin x/x at-
tenuation due to the 8 kHz sample and hold.
The filter is then followed by a 2nd order RC ac-
tive post-filter and power amplifier capable of driv-
ing a 600

load to a level of 7.2 dBm. The re-

ceive section is unity-gain. Upon the occurence of
FS

, the data at the D

input is clocked in on the

falling edge of the next eight BCLK

(BCLK

) pe-

riods. At the end of the decoder time slot, the de-
coding cycle begins, and 10

s later the decoder

DAC output is updated. The total decoder delay
is

s (decoder update) plus 110

s (filter

delay) plus 62.5

s (1/2 frame), which gives ap-

proximately 180

s. A mute circuitry is a active

during 10ms when power up.

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

to GNDA

, V

OUT

Voltage at any Analog Input or Output

+ 0.3 to V

0.3

Voltage at Any Digital Input or Output

+ 0.3 to GNDA 0.3

oper

Operating Temperature Range

25 to + 125

stg

Storage Temperature Range

65 to + 150

Lead Temperature (soldering, 10 seconds)

300

ELECTRICAL OPERATING CHARACTERISTICS V

= 5.0 V

5 %, V

= 5.0 V

5%GNDA = 0 V,

= 0

C to 70

C; Typical Characteristics Specified at V

= 5.0 V, V

= 5.0 V, T

= 25

C ; all signals

are referenced to GNDA.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Input Low Voltage

0.6

Input High Voltage

2.2

Output Low Voltage
I

= 3.2mA D

= 3.2mA, Open Drain TS

0.4
0.4

V
V

Output High Voltage
I

= 3.2mA D

2.4

Input Low Current (GNDA

, all digital inputs)

Input High Current (V

) except BCLK

/BCLKSEL

Output Current in HIGH Impedance State (TRI-STATE)
(GNDA

) D

ETC5054 - ETC5057

5/18

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