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September 2001
s
SET - RESET CAPABILITY
s
STATIC FLIP-FLOP OPERATION - RETAINS
STATE INDEFINITELY WITH CLOCK LEVEL
EITHER "HIGH" OR "LOW"
s
MEDIUM SPEED OPERATION 16MHz (TYP.)
CLOCK TOGGLE RATE AT 10V
s
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
s
QUIESCENT CURRENT SPECIFIED UP TO
20V
s
5V, 10V AND 15V PARAMETRIC RATINGS
s
INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25C
s
100% TESTED FOR QUIESCENT CURRENT
s
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
The HCF4013B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4013B consists of two identical,
independent data type flip-flops. Each flip-flop has
independent data, set, reset, and clock inputs and
Q and Q outputs. This device can be used for shift
register applications, and, by connecting Q output
to the data input, for counter and toggle
applications. The logic level present at the D input
is transferred to the Q output during the
positive-going transition of the clock pulse. Setting
or resetting is independent of the clock and is
accomplished by a high level on the set or reset
line, respectively
HCF4013B
DUAL D-TYPE FLIP FLOP
PIN CONNECTION
ORDER CODES
PACKAGE
TUBE
T & R
DIP
HCF4013BEY
SOP
HCF4013BM1
HCF4013M013TR
DIP
SOP
HCF4013B
2/9
INPUT EQUIVALENT CIRCUIT
LOGIC DIAGRAM
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
:
Low Level
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V
SS
pin voltage.
RECOMMENDED OPERATING CONDITIONS
PIN No
SYMBOL
NAME AND FUNCTION
3, 11
CLOCK1
CLOCK2
Clock Inputs
4, 10
RESET1
RESET2
Reset Inputs
6, 8
SET1, SET2 Set Inputs
5, 9
D1, D2
Data Inputs
1, 13
Q1, Q2
Data Outputs
2, 12
Q1, Q2
Data Outputs
7
V
SS
Negative Supply Voltage
14
V
DD
Positive Supply Voltage
CLOCK
D
RESET
SET
Q
Q
L
L
L
L
H
H
L
L
H
L
X
L
L
Q
Q
X
X
H
L
L
H
X
X
L
H
H
L
X
X
H
H
H
H
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
-0.5 to +22
V
V
I
DC Input Voltage
-0.5 to V
DD
+ 0.5
V
I
I
DC Input Current
10
mA
P
D
Power Dissipation per Package
200
mW
Power Dissipation per Output Transistor
100
mW
T
op
Operating Temperature
-55 to +125
C
T
stg
Storage Temperature
-65 to +150
C
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
3 to 20
V
V
I
Input Voltage
0 to V
DD
V
T
op
Operating Temperature
-55 to 125
C
HCF4013B
3/9
DC SPECIFICATIONS
The Noise Margin for both "1" and "0" level is: 1V min. with V
DD
=5V, 2V min. with V
DD
=10V, 2.5V min. with V
DD
=15V
Symbol
Parameter
Test Condition
Value
Unit
V
I
(V)
V
O
(V)
|I
O
|
(
A)
V
DD
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
I
L
Quiescent Current
0/5
5
0.02
1
30
30
A
0/10
10
0.02
2
60
60
0/15
15
0.02
4
120
120
0/20
20
0.04
20
600
600
V
OH
High Level Output
Voltage
0/5
<1
5
4.95
4.95
4.95
V
0/10
<1
10
9.95
9.95
9.95
0/15
<1
15
14.95
14.95
14.95
V
OL
Low Level Output
Voltage
5/0
<1
5
0.05
0.05
0.05
V
10/0
<1
10
0.05
0.05
0.05
15/0
<1
15
0.05
0.05
0.05
V
IH
High Level Input
Voltage
0.5/4.5
<1
5
3.5
3.5
3.5
V
1/9
<1
10
7
7
7
1.5/13.5
<1
15
11
11
11
V
IL
Low Level Input
Voltage
4.5/0.5
<1
5
1.5
1.5
1.5
V
9/1
<1
10
3
3
3
13.5/1.5
<1
15
4
4
4
I
OH
Output Drive
Current
0/5
2.5
<1
5
-1.36
-3.2
-1.15
-1.1
mA
0/5
4.6
<1
5
-0.44
-1
-0.36
-0.36
0/10
9.5
<1
10
-1.1
-2.6
-0.9
-0.9
0/15
13.5
<1
15
-3.0
-6.8
-2.4
-2.4
I
OL
Output Sink
Current
0/5
0.4
<1
5
0.44
1
0.36
0.36
mA
0/10
0.5
<1
10
1.1
2.6
0.9
0.9
0/15
1.5
<1
15
3.0
6.8
2.4
2.4
I
I
Input Leakage
Current
0/18
Any Input
18
10
-5
0.1
1
1
A
C
I
Input Capacitance
Any Input
5
7.5
pF
HCF4013B
4/9
DYNAMIC ELECTRICAL CHARACTERISTICS (T
amb
= 25C, C
L
= 50pF, R
L
= 200K
, t
r
= t
f
= 20 ns)
(*) Typical temperature coefficient for all V
DD
value is 0.3 %/C.
(1) Input tr, tf = 5ns
(2) If more than unit is cascaded in a parallel clocked application, tr should be made less than or equal to the sum of the fixed propagation
delay time at 15pF and the transition time of the carry output driving stage for the estimated capacitive load.
Symbol
Parameter
Test Condition
Value (*)
Unit
V
DD
(V)
Min.
Typ.
Max.
t
TLH
t
THL
Propagation Delay Time
(CLOCK to Q or Q outputs)
5
150
300
ns
10
65
130
15
45
90
t
PLH
Propagation Delay Time
(SET to Q or RESET to Q)
5
150
300
ns
10
65
130
15
45
90
t
PHL
Propagation Delay
Time(SET to Q or RESET
to Q)
5
200
400
ns
10
85
170
15
60
120
t
THL
t
TLH
Transition Time
5
100
200
ns
10
50
100
15
40
80
f
CL
(1)
Maximum Clock Input
Frequency
5
3.5
7
MHz
10
8
16
15
12
24
t
W
Clock Pulse Width
5
140
70
ns
10
60
30
15
40
20
t
r
, t
f
(2)
Clock Input Rise or Fall
Time
5
15
s
10
4
15
1
t
W
Set or Reset Pulse Width
5
180
90
ns
10
80
40
15
50
25
t
setup
Data Setup Time
5
40
20
ns
10
20
10
15
15
7
HCF4013B
5/9
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= 200K
R
T
= Z
OUT
of pulse generator (typically 50
)
WAVEFORM 1 : CLOCK TO Qn, Qn PROPAGATION DELAY TIMES, Dn TO CLOCK SETUP AND
HOLD TIMES, CLOCK MINIMUM PULSE WITDH, MAXIMUM CLOCK FREQUENCY
(f=1MHz; 50% duty cycle)
HCF4013B
6/9
WAVEFORM 2 : PROPAGATION DELAY TIMES (Qn, Qn TO SET, RESET), MINIMUM PULSE WIDTH
(SET AND RESET) (f=1MHz; 50% duty cycle)
HCF4013B
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DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
a1
0.51
0.020
B
1.39
1.65
0.055
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
15.24
0.600
F
7.1
0.280
I
5.1
0.201
L
3.3
0.130
Z
1.27
2.54
0.050
0.100
Plastic DIP-14 MECHANICAL DATA
P001A
HCF4013B
8/9
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
1.75
0.068
a1
0.1
0.2
0.003
0.007
a2
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45 (typ.)
D
8.55
8.75
0.336
0.344
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
7.62
0.300
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
0.68
0.026
S
8 (max.)
SO-14 MECHANICAL DATA
PO13G
HCF4013B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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