1/10
September 2002
s
MEDIUM SPEED OPERATION 12 MHz (Typ.)
CLOCK RATE AT V
DD
- V
SS
= 10V
s
FULLY STATIC OPERATION
s
8 MASTER-SLAVE FLIP-FLOPS PLUS
INPUT AND OUTPUT BUFFERING
s
HIGH NOISE IMMUNITY
s
QUIESCENT CURRENT SPECIFIED UP TO
20V
s
5V, 10V AND 15V PARAMETRIC RATINGS
s
INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25C
s
100% TESTED FOR QUIESCENT CURRENT
s
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF4015B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4015B consists of two identical, independent,
4 stage serial-input/parallel-output registers.
Each register has independent CLOCK and
RESET inputs as well as a single serial DATA
input. "Q" outputs are available from each of the
four stages on both registers. All register stages
are D-TYPE, MASTER-SLAVE flip-flops. The
logic level present at the DATA input is transferred
into the first register stage and shifted over one
stage at each positive going clock transition. The
resetting of all stages is accomplished by a high
level on the reset line. It is possible to expand the
register to 8 stages using one HCF4015B
package and to expand to more than 8 stages by
using addition HCF4015Bs.
HCF4015B
DUAL 4-STAGE STATIC SHIFT REGISTER WITH
SERIAL INPUT/PARALLEL OUTPUT
PIN CONNECTION
ORDER CODES
PACKAGE
TUBE
T & R
DIP
HCF4015BEY
SOP
HCF4015BM1
HCF4015M013TR
DIP
SOP
HCF4015B
2/10
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
FUNCTIONAL DIAGRAM
TRUTH TABLE
X : Don't Care
PIN No
SYMBOL
NAME AND FUNCTION
1, 9
CLOCK A
CLOCK B
Clock Input
6, 14
RESET A
RESET B
Reset Input
7, 15
DATA A
DATA B
Data Inputs
5, 4, 3, 10
QnA
Outputs A-Stage
13, 12, 11, 2
QnB
Outpus B-Stage
8
V
SS
Negative Supply Voltage
16
V
DD
Positive Supply Voltage
CLOCK
D
R
Q
1
Q
n
L
L
L
Q
n
- 1
H
L
H
Q
n
- 1
X
L
Q
1
Q
n
- (NO CHANGE)
X
X
H
L
0
HCF4015B
3/10
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V
SS
pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
-0.5 to +22
V
V
I
DC Input Voltage
-0.5 to V
DD
+ 0.5
V
I
I
DC Input Current
10
mA
P
D
Power Dissipation per Package
200
mW
Power Dissipation per Output Transistor
100
mW
T
op
Operating Temperature
-55 to +125
C
T
stg
Storage Temperature
-65 to +150
C
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
3 to 20
V
V
I
Input Voltage
0 to V
DD
V
T
op
Operating Temperature
-55 to 125
C
HCF4015B
4/10
DC SPECIFICATIONS
The Noise Margin for both "1" and "0" level is: 1V min. with V
DD
=5V, 2V min. with V
DD
=10V, 2.5V min. with V
DD
=15V
Symbol
Parameter
Test Condition
Value
Unit
V
I
(V)
V
O
(V)
|I
O
|
(
A)
V
DD
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
I
L
Quiescent Current
0/5
5
0.04
5
150
150
A
0/10
10
0.04
10
300
300
0/15
15
0.04
20
600
600
0/20
20
0.08
100
3000
3000
V
OH
High Level Output
Voltage
0/5
<1
5
4.95
4.95
4.95
V
0/10
<1
10
9.95
9.95
9.95
0/15
<1
15
14.95
14.95
14.95
V
OL
Low Level Output
Voltage
5/0
<1
5
0.05
0.05
0.05
V
10/0
<1
10
0.05
0.05
0.05
15/0
<1
15
0.05
0.05
0.05
V
IH
High Level Input
Voltage
0.5/4.5
<1
5
3.5
3.5
3.5
V
1/9
<1
10
7
7
7
1.5/13.5
<1
15
11
11
11
V
IL
Low Level Input
Voltage
4.5/0.5
<1
5
1.5
1.5
1.5
V
9/1
<1
10
3
3
3
13.5/1.5
<1
15
4
4
4
I
OH
Output Drive
Current
0/5
2.5
<1
5
-1.36
-3.2
-1.1
-1.1
mA
0/5
4.6
<1
5
-0.44
-1
-0.36
-0.36
0/10
9.5
<1
10
-1.1
-2.6
-0.9
-0.9
0/15
13.5
<1
15
-3.0
-6.8
-2.4
-2.4
I
OL
Output Sink
Current
0/5
0.4
<1
5
0.44
1
0.36
0.36
mA
0/10
0.5
<1
10
1.1
2.6
0.9
0.9
0/15
1.5
<1
15
3.0
6.8
2.4
2.4
I
I
Input Leakage
Current
0/18
Any Input
18
10
-5
0.1
1
1
A
C
I
Input Capacitance
Any Input
5
7.5
pF
HCF4015B
5/10
DYNAMIC ELECTRICAL CHARACTERISTICS (T
amb
= 25C, C
L
= 50pF, R
L
= 200K
, t
r
= t
f
= 20 ns)
(*) Typical temperature coefficient for all V
DD
value is 0.3 %/C.
(1) If more than one unit is cascaded in the parallel clocked application, t
r
CL should be made less than or equal to the sum of the fixed prop-
agation delay at 15 pF and the transmission time of the carry output driving stage of the estimated capacitive load.
Symbol
Parameter
Test Condition
Value (*)
Unit
V
DD
(V)
Min.
Typ.
Max.
CLOCKED OPERATION
t
PLH
t
PHL
Propagation Delay Time
(carry out or decoded out
lines)
5
160
320
ns
10
80
160
15
60
120
t
THL
t
TLH
Transition Time (carry out
or decoded out lines)
5
100
200
ns
10
50
100
15
40
80
f
CL
Maximum Clock Input
Frequency
5
3
6
MHz
10
6
12
15
8.5
17
t
W
Clock Pulse Width
5
180
90
ns
10
80
40
15
50
25
t
r
, t
f
(1)
Clock Input Rise or Fall
Time
5
15
s
10
15
15
15
t
setup
Data Setup Time
5
70
35
ns
10
40
20
15
30
15
RESET OPERATION
t
PLH,
t
PHL
Propagation Delay Time
5
200
400
ns
10
100
200
15
80
160
t
W
Reset Pulse Width
5
200
100
ns
10
80
40
15
60
30
HCF4015B
6/10
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= 200K
R
T
= Z
OUT
of pulse generator (typically 50
)
WAVEFORM 1 : MINIMUM PULSE WIDTH, PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
HCF4015B
7/10
WAVEFORM 2 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle)
HCF4015B
8/10
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
a1
0.51
0.020
B
0.77
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
3.3
0.130
Z
1.27
0.050
Plastic DIP-16 (0.25) MECHANICAL DATA
P001C
HCF4015B
9/10
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
1.75
0.068
a1
0.1
0.2
0.003
0.007
a2
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45 (typ.)
D
9.8
10
0.385
0.393
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
0.62
0.024
S
(max.)
SO-16 MECHANICAL DATA
PO13H
8
HCF4015B
10/10
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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