1/11
September 2001
s
COUNTER AND 7-SEGMENT DECODING IN
ONE PACKAGE
s
EASILY INTERFACED WITH 7-SEGMENT
DISPLAY TYPES
s
FULLY STATIC COUNTER OPERATION : DC
TO 6MHz (Typ.) AT V
DD
= 10V
s
IDEAL FOR LOW POWER DISPLAYS
s
DISPLAY ENABLE OUTPUT
s
QUIESCENT CURRENT SPECIF. UP TO 20V
s
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
s
INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25C
s
100% TESTED FOR QUIESCENT CURRENT
s
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
The HCF4026B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4026B consists of a 5-stages Johnson
decade counter and an output decoder which
converts the Johnson code to a 7 segment
decoded output for driving one stage in a
numerical display. This device is particularly
advantageous in display applications where low
power dissipation and/or low package count are
important. This device has CLOCK, RESET,
CLOCK INHIBIT, DISPLAY ENABLE input and
CARRY OUT, DISPLAY ENABLE, UNGATED "C"
SEGMENT and 7 DECODED outputs (a to g).
A high RESET signal clears the decade counter to
its zero count. The counter is advanced one count
at the positive clock signal transition if the CLOCK
INHIBIT signal is low. Counter advancement via
the clock line is inhibited when the CLOCK
INHIBIT signal is high. Antilock gating is provided
on the JOHNSON counter, thus assuring proper
counting sequence. The CARRY-OUT (C
OUT
)
signal completes one cycle every ten CLOCK
INPUT cycles and is used to clock the succeeding
decade directly in a multi-decade counting chain.
HCF4026B
DECADE COUNTER/DIVIDER WITH DECODED
7-SEGMENT DISPLAY OUTPUT AND DISPLAY ENABLE
PIN CONNECTION
ORDER CODES
PACKAGE
TUBE
T & R
DIP
HCF4026BEY
SOP
HCF4026BM1
HCF4026M013TR
DIP
SOP
HCF4026B
2/11
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
FUNCTIONAL DIAGRAM
PIN No
SYMBOL
NAME AND FUNCTION
1
CLOCK
Clock Input
10, 12, 13, 9,
11, 6, 7
a to g
7 - Segments Decoded
Outputs
2
CLOCK
INHIBIT
Clock Inhibit Input
15
RESET
Reset Input
3
DISPLAY
ENABLE IN
Display Enable Input
5
CARRY OUT Carry Out Output
4
DISPLAY
ENABLE
OUT
Display Enable Output
14
UNGATED
"C" SEG-
MENT OUT
Ungated "C" Segment
Output
8
V
SS
Negative Supply Voltage
16
V
DD
Positive Supply Voltage
The seven decoded outputs (a, b, c, d, e, f, g)
illuminate the proper segments in a seven
segment display device used for representing the
decimal numbers 0 to 9. The 7-segment outputs
go high when the DISPLAY ENABLE IN is high.
When the DISPLAY ENABLE IN is low the seven
decoded outputs are forced low regardless of the
state of the counter. Activation of the display only
when required results in significant power savings.
This system also facilitates implementation of
display character multiplexing. The CARRY OUT
and UNGATED "C" SEGMENT signals are not
gated by the DISPLAY ENABLE and therefore are
available continuously. This feature is a
requirement in implementation of certain divider
function such a as divide by 60 and divide by 12.
HCF4026B
3/11
LOGIC DIAGRAM
TIMING CHART
HCF4026B
4/11
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V
SS
pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
-0.5 to +22
V
V
I
DC Input Voltage
-0.5 to V
DD
+ 0.5
V
I
I
DC Input Current
10
mA
P
D
Power Dissipation per Package
200
mW
Power Dissipation per Output Transistor
100
mW
T
op
Operating Temperature
-55 to +125
C
T
stg
Storage Temperature
-65 to +150
C
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
3 to 20
V
V
I
Input Voltage
0 to V
DD
V
T
op
Operating Temperature
-55 to 125
C
HCF4026B
5/11
DC SPECIFICATIONS
The Noise Margin for both "1" and "0" level is: 1V min. with V
DD
=5V, 2V min. with V
DD
=10V, 2.5V min. with V
DD
=15V
Symbol
Parameter
Test Conditions
Value
Unit
V
I
(V)
V
O
(V)
I
O
(
A)
V
DD
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
I
L
Quiescent Current
0/5
5
0.04
5
150
150
A
0/10
10
0.04
10
300
300
0/15
15
0.04
20
600
600
0/20
20
0.08
100
3000
3000
V
OH
High Level Output
Voltage
0/5
<1
5
4.95
4.95
4.95
V
0/10
<1
10
9.95
9.95
9.95
0/15
<1
15
14.95
14.95
14.95
V
OL
Low Level Output
Voltage
5/0
<1
5
0.05
0.05
0.05
V
10/0
<1
10
0.05
0.05
0.05
15/0
<1
15
0.05
0.05
0.05
V
IH
High Level Input
Voltage
0.5/4.5
<1
5
3.5
3.5
3.5
V
1/9
<1
10
7
7
7
1.5/18.5
<1
15
11
11
11
V
IL
Low Level Input
Voltage
0.5/4.5
<1
5
1.5
1.5
1.5
V
9/1
<1
10
3
3
3
1.5/18.5
<1
15
4
4
4
I
OH
Output Drive
Current
0/5
2.5
5
-1.36
-3.2
-1.1
-1.1
mA
0/5
4.6
5
-0.44
-1
-0.36
-0.36
0/10
9.5
10
-1.1
-2.6
-0.9
-0.9
0/15
13.5
15
-3.0
-6.8
-2.4
-2.4
I
OL
Output Sink
Current
0/5
0.4
5
0.44
1
0.36
0.36
mA
0/10
0.5
10
1.1
2.6
0.9
0.9
0/15
1.5
15
3.0
6.8
2.4
2.4
I
I
Input Leakage
Current
0/18
any input
18
10
-5
0.1
1
1
A
C
I
Input Capacitance
any input
5
7.5
pF
HCF4026B
6/11
DYNAMIC ELECTRICAL CHARACTERISTICS (T
amb
= 25C, C
L
= 50pF, R
L
= 200K
, t
r
= t
f
= 20 ns)
(*) Typical temperature coefficient for all V
DD
value is 0.3 %/C.
(1) Measured with respect to carry output line.
Symbol
Parameter
Test Condition
Value (*)
Unit
V
DD
(V)
Min.
Typ.
Max.
CLOCKED OPERATION
t
PLH
t
PHL
Propagation Delay Time
(Carry Out Line)
5
250
500
ns
10
100
200
15
75
150
t
PLH
t
PHL
Propagation Delay Time
(Decoded Out Lines)
5
350
700
ns
10
125
250
15
90
180
t
THL
t
TLH
Transition Time
(Carry Out Line)
5
100
200
ns
10
50
100
15
25
50
f
CL
(1)
Maximum Clock Input
Frequency
5
2.5
5
MHz
10
5.5
11
15
8
16
t
WC
Clock Pulse Width
5
110
260
ns
10
50
100
15
40
80
t
r
, t
f
Clock Input Rise or Fall
Time
5
Unlimited
s
10
15
RESET OPERATION
t
PLH
t
PHL
Propagation Delay Time
(Carry Out Line)
5
275
550
ns
10
120
240
15
80
160
t
PLH
t
PHL
Propagation Delay Time
(Decoded Out Lines)
5
300
600
ns
10
125
250
15
90
180
t
WR
Reset Pulse Widht
5
100
120
ns
10
50
100
15
25
50
t
rem
Reset Removal Time
5
0
30
ns
10
0
15
15
0
10
HCF4026B
7/11
TYPICAL APPLICATIONS
Interfacing with Filament Fluorescent Display
Interfacing with LED Displays (display common
anode)
Interfacing with NIXIE Tube
Detail of Typical Flip-flop Stage
Interfacing with LED Displays (display common
cathode)
HCF4026B
8/11
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= 200K
R
T
= Z
OUT
of pulse generator (typically 50
)
HCF4026B
9/11
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
a1
0.51
0.020
B
0.77
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
3.3
0.130
Z
1.27
0.050
Plastic DIP-16 (0.25) MECHANICAL DATA
P001C
HCF4026B
10/11
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
1.75
0.068
a1
0.1
0.2
0.003
0.007
a2
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45 (typ.)
D
9.8
10
0.385
0.393
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
0.62
0.024
S
8 (max.)
SO-16 MECHANICAL DATA
PO13H
HCF4026B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2001 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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11/11
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