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September 2002
s
SET RESET CAPABILITY
s
STATIC FLIP-FLOP OPERATION - RETAINS
STATE INDEFINETELY WITH CLOCK LEVEL
EITHER "HIGH" OR "LOW"
s
MEDIUM-SPEED OPERATION - 16MHz
(Typ. clock toggle rate at 10V)
s
QUIESCENT CURRENT SPECIFIED UP TO
20V
s
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
s
5V, 10V AND 15V PARAMETRIC RATINGS
s
INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25C
s
100% TESTED FOR QUIESCENT CURRENT
s
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF4027B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4027B is a single monolithic chip integrated
circuit containing two identical
complementary-symmetry J-K master-slave
flip-flops. Each flip-flop has provisions for
individual J, K, Set, Reset, and Clock input
signals. Buffered Q and Q signals are provided as
outputs. This input-output arrangement provides
for compatible operation with the HCF4013B dual
D type flip-flop.
This device is useful in performing control,
register, and toggle functions. Logic levels present
at the J and K inputs, along with internal
self-steering, control the state of each flip-flop;
changes in the flip-flop state are synchronous with
the positive-going transition of the clock pulse. Set
and Reset functions are independent of the clock
and are initiated when a high level signal is
present at either the Set or Reset input.
HCF4027B
DUAL J-K MASTER SLAVE FLIP-FLOP
PIN CONNECTION
ORDER CODES
PACKAGE
TUBE
T & R
DIP
HCF4027BEY
SOP
HCF4027BM1
HCF4027M013TR
DIP
SOP
HCF4027B
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LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V
SS
pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
-0.5 to +22
V
V
I
DC Input Voltage
-0.5 to V
DD
+ 0.5
V
I
I
DC Input Current
10
mA
P
D
Power Dissipation per Package
200
mW
Power Dissipation per Output Transistor
100
mW
T
op
Operating Temperature
-55 to +125
C
T
stg
Storage Temperature
-65 to +150
C
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
3 to 20
V
V
I
Input Voltage
0 to V
DD
V
T
op
Operating Temperature
-55 to 125
C
HCF4027B
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DYNAMIC ELECTRICAL CHARACTERISTICS (T
amb
= 25C, C
L
= 50pF, R
L
= 200K
, t
r
= t
f
= 20 ns)
(*) Typical temperature coefficient for all V
DD
value is 0.3 %/C.
(1) Input t
r
, t
f
= 5ns
Symbol
Parameter
Test Condition
Value (*)
Unit
V
DD
(V)
Min.
Typ.
Max.
t
PLH
t
PHL
Propagation Delay
Time(Clock to Q or Q
Outputs)
5
150
300
ns
10
65
130
15
45
90
t
PLH
Propagation Delay Time
(Set to Q or Reset to Q)
5
150
300
ns
10
65
130
15
45
90
t
PHL
Propagation Delay Time
(Set to Q or Reset to Q)
5
200
400
ns
10
85
170
15
60
120
t
TLH
t
THL
Transition Time
5
100
200
ns
10
50
100
15
40
80
t
W
Pulse Width (Clock)
5
140
70
ns
10
60
30
15
40
20
t
W
Pulse Width (Set or Reset)
5
180
90
ns
10
80
40
15
50
25
t
r,
t
f
Clock input Rise or Fall
Time
5
15
s
10
4
15
1
t
setup
Setup Time (DATA)
5
200
100
ns
10
75
35
15
50
25
f
MAX
Maximum Clock Input
Frequency
(1)
(toggle mode)
5
3.5
7
MHz
10
8
16
15
12
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