1/11
September 2001
s
4 STAGE CLOCKED SHIFT OPERATION
s
SYNCHRONOUS PARALLEL ENTRY ON
ALL 4 STAGES
s
JK INPUTS ON FIRST STAGE
s
ASYNCHRONOUS TRUE/COMPLEMENT
CONTROL ON ALL OUTPUTS
s
STATIC FLIP-FLOP OPERATION;
MASTER-SLAVE CONFIGURATION
s
BUFFERED INPUTS AND OUTPUTS
s
HIGH SPEED 12MHz (Typ.) at V
DD
= 10V
s
QUIESCENT CURRENT SPECIF. UP TO 20V
s
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
s
5V, 10V AND 15V PARAMETRIC RATINGS
s
INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25C
s
100% TESTED FOR QUIESCENT CURRENT
s
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
The HCF4035B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
This device is a four stage clocked signal serial
register with provision for synchronous
PARALLEL inputs to each stage and SERIAL
inputs to the first stage via JK logic. Register
stages 2, 3, and 4 are coupled in a serial D flip-flop
configuration when the register is in the serial
mode (PARALLEL/SERIAL control low). Parallel
entry into each register stage is permitted when
the PARALLEL/SERIAL control is high. In the
parallel or serial mode information is transferred
on positive clock transitions. When the TRUE/
COMPLEMENT control is high, the true contents
of the register are available at the output
terminals. When the TRUE/COMPLEMENT
control is low, the outputs are the complements of
the data in the register. The TRUE/
COMPLEMENT control functions asynchronously
with respect to the CLOCK signal. JK input logic is
provided on the first stage SERIAL input to
minimize logic requirements particularly in
counting and sequence generation applications.
With JK inputs connected together, the first stage
becomes a D flip-flop. An asynchronous common
RESET is also provided.
HCF4035B
4 STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER
PIN CONNECTION
ORDER CODES
PACKAGE
TUBE
T & R
DIP
HCF4035BEY
SOP
HCF4035BM1
HCF4035M013TR
DIP
SOP
HCF4035B
3/11
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V
SS
pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
-0.5 to +22
V
V
I
DC Input Voltage
-0.5 to V
DD
+ 0.5
V
I
I
DC Input Current
10
mA
P
D
Power Dissipation per Package
200
mW
Power Dissipation per Output Transistor
100
mW
T
op
Operating Temperature
-55 to +125
C
T
stg
Storage Temperature
-65 to +150
C
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
3 to 20
V
V
I
Input Voltage
0 to V
DD
V
T
op
Operating Temperature
-55 to 125
C
HCF4035B
5/11
DYNAMIC ELECTRICAL CHARACTERISTICS (T
amb
= 25C, C
L
= 50pF, R
L
= 200K
, t
r
= t
f
= 20 ns)
(*) Typical temperature coefficient for all V
DD
value is 0.3 %/C.
Symbol
Parameter
Test Condition
Value (*)
Unit
V
DD
(V)
Min.
Typ.
Max.
CLOCKED OPERATION
t
PLH
t
PHL
Propagation Delay Time
5
250
500
ns
10
100
200
15
75
150
t
THL
t
TLH
Transition Time
5
100
200
ns
10
50
100
15
40
80
f
MAX
Maximum Clock Input
Frequency
5
2
4
MHz
10
6
12
15
8
16
t
W
Clock Pulse Width
5
100
200
ns
10
45
90
15
30
60
t
r
, t
f
Clock Input Rise or Fall
Time
5
15
s
10
15
15
15
t
setup
Data Setup Time J/K lines
5
110
220
ns
10
40
80
15
30
60
t
setup
Data Setup Time
Parallel In Lines
5
70
140
ns
10
25
50
15
20
40
RESET OPERATION
t
PLH
t
PHL
Propagation Delay Time
5
230
460
ns
10
100
200
15
80
160
t
W
Reset Pulse Width
5
125
250
ns
10
55
110
15
40
40
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