1/12
September 2001
s
QUIESCENT CURRENT SPECIFIED UP TO
20V
s
VERY LOW POWER CONSUMPTION : 70
W
(TYP.) AT VCO f
o
= 10kHz, V
DD
= 5V
s
OPERATING FREQUENCY RANGE : UP TO
1.4MHz (TYP.) AT V
DD
= 10V
s
LOW FREQUENCY DRIFT : 0.04%/C (typ.)
AT V
DD
= 10V
s
CHOICE OF TWO PHASE COMPARATORS :
1) EXCLUSIVE - OR NETWORK
2) EDGE-CONTROLLED MEMORY
NETWORK WITH PHASE-PULSE OUTPUT
FOR LOCK INDICATION
s
HIGH VCO LINEARITY: <1% (TYP.)
s
VCO INHIBIT CONTROL FOR ON-OFF
KEYING AND ULTRA-LOW STANDBY
POWER CONSUMPTION
s
SOURCE-FOLLOWER OUTPUT OF VCO
CONTROL INPUT (demod. output)
s
ZENER DIODE TO ASSIST SUPPLY
REGULATION
s
5V, 10V AND 15V PARAMETRIC RATINGS
s
INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25C
s
100% TESTED FOR QUIESCENT CURRENT
s
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
The HCF4046B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
Technology, available in 16-lead dual in-line
plastic or ceramic package. The HCF4046B
CMOS Micropower Phase-Locked Loop (PLL)
consists of a low-power, linear voltage-controlled
oscillator (VCO) and two different phase
comparators having a common signal-input
amplifier and a common comparator input. A 5.2V
zener diode is provided for supply regulation if
necessary.
HCF4046B
MICROPOWER PHASE-LOCKED LOOP
PIN CONNECTION
ORDER CODES
PACKAGE
TUBE
T & R
DIP
HCF4046BEY
SOP
HCF4046BM1
HCF4046M013TR
DIP
SOP
HCF4046B
2/12
VCO Section
The VCO requires one external capacitor C1 and
one or two external resistors (R1 or R1 and R2).
Resistor R1 and capacitor C1 determine the
frequency range of the VCO and resistor R2
enables the VCO to have a frequency offset if
required. The high input impedance (10
12
) of the
VCO simplifiers the design of low-pass filters by
permitting the designer a wide choice of
resistor-to-capacitor ratios. In order not to load the
low-pass filter, a source-follower output of the
VCO input voltage is provided at terminal 10
(DEMODULATED OUTPUT). If this terminal is
used, a load resistor (R
S
) of 10 K
or more should
be connected from this terminal to V
SS
. If unused
this terminal should be left open. The VCO can be
connected either directly or through frequency
dividers to the comparator input of the phase
comparators. A full CMOS logic swing is available
at the output of the VCO and allows direct
coupling to CMOS frequency dividers such as the
HCF4024B, HCF4018B, HCF4020B, HCF4022B,
HCF4029B and HBF4059A. One or more
HCF4018B (Presettable Divide-by-N Counter) or
HCF4029B (Presettable Up/Down Counter), or
HBF4059A (Programmable Divide-by-"N"
Counter), together with the HCF4046B
(Phase-Locked Loop) can be used to build a
micropower low-frequency synthesizer. A logic 0
on the INHIBIT input "enables" the VCO and the
source follower, while a logic 1 "turns off" both to
minimize stand-by power consumption.
Phase Comparators
The phase-comparator signal input (terminal 14)
can be direct-coupled provided the signal swing is
within CMOS logic levels [logic "0"
30% of
(V
DD
-V
SS
), logic "1"
70% of (V
DD
-V
SS
)]. For
smaller swings the signal must be capacitively
coupled to the self-biasing amplifier at the signal
input. Phase comparator I is an exclusive-OR
network; it operates analagously to an over-driven
balanced mixer. To maximize the lock range, the
signal-and comparator-input frequencies must
have a 50% duty cycle. With no signal or noise on
the signal input, this phase comparator has an
average output voltage equal to V
DD
/2. The
low-pass filter connected to the output of phase
comparator I supplies the averaged voltage to the
VCO input, and causes the VCO to oscillate at the
center frequency (fo). The frequency range of
input signals on which the PLL will lock if it was
initially out of lock is defined as the frequency
capture range (2 f
C
). The frequency range of input
signals on which the loop will stay locked if it was
initially in lock is defined as the frequency lock
range (2 f
L
). The capture range is
the lock range.
With phase comparator I the range of frequencies
over which the PLL can acquire lock (capture
range) is dependent on the low-pass-filter
characteristics, and can be made as large as the
lock range. Phase-comparator I enables a PLL
system to remain in lock in spite of high amounts
of noise in the input signal. One characteristic of
this type of phase comparator is that it may lock
onto input frequencies that are close to harmonics
of the VCO center-frequency. A second
characteristic is that the phase angle between the
signal and the comparator input varies between 0
and 180, and is 90 at the center frequency. Fig.1
shows the typical, triangular, phase-to-output
response characteristic of phase-comparator I.
Typical waveforms for a CMOS
phase-locked-loop employing phase comparator I
in locked condition of fo is shown in fig.2.
Phase-comparator II is an edge-controlled digital
memory network. It consists of four flip-flop
stages, control gating, and a three-stage
output-circuit comprising p- and n-type drivers
having a common output node. When the p-MOS
or n-MOS drivers are ON they pull the output up to
V
DD
or down to V
SS
, respectively. This type of
phase comparator acts only on the positive edges
of the signal and comparator inputs. The duty
cycles of the signal and comparator inputs are not
important since positive transitions control the PLL
system utilizing this type of comparator. If the
signal-input frequency is higher than the
comparator-input frequency, the p-type output
driver is maintained ON most of the time, and both
the n- and p-drivers OFF (3 state) the remainder of
the time. If the signal-input frequency is lower than
the comparator-input frequency, the n-type output
driver is maintained ON most of the time, and both
the n- and p-drivers OFF (3 state) the remainder of
the time. If the signal and comparator-input
frequencies are the same, but the signal input lags
the comparator input in phase, the n-type output
driver is maintained ON for a time corresponding
to the phase difference. If the signal and
comparator-input frequencies are the same, but
the comparator input lags the signal in phase, the
HCF4046B
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p-type output driver is maintained ON for a time
corresponding to the phase difference.
Subsequently, the capacitor voltage of the
low-pass filter connected to this phase comparator
is adjusted until the signal and comparator inputs
are equal in both phase and frequency. At this
stable point both p- and n-type output drivers
remain OFF and thus the phase comparator
output becomes an open circuit and holds the
voltage on the capacitor of the low-pass filter
constant. Moreover the signal at the "phase
pulses" output is a high level which can be used
for indicating a locked condition. Thus, for phase
comparator II, no phase difference exists between
signal and comparator input over the full VCO
frequency range. Moreover, the power dissipation
due to the low-pass filter is reduced when this type
of phase comparator is used because both the p-
and n-type output drivers are OFF for most of the
signal input cycle. It should be noted that the PLL
lock range for this type of phase comparator is
equal to the capture range, independent of the
low-pass filter. With no signal present at the signal
input, the VCO is adjusted to its lowest frequency
for phase comparator II. Fig.3 shows typical
waveforms for a CMOS PLL employing phase
comparator II in a locked condition.
Figure 1 : Phase-Comparator I Characteristics at Low-Pass Filter Output.
Figure 2 : Typical Waveforms for CMOS Phase Locked-Loop Employing Phase Comparator I in Locked
Condition of f
o
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