1/13
L6569
L6569A
June 2000
This is preliminary information on a new product now in development. Details are subject to change without notice.
s
HIGH VOLTAGE RAIL UP TO 600V
s
BCD OFF LINE TECHNOLOGY
s
INTERNAL BOOTSTRAP DIODE
STRUCTURE
s
15.6V ZENER CLAMP ON V
S
s
DRIVER CURRENT CAPABILITY:
- SINK CURRENT = 270mA
- SOURCE CURRENT = 170mA
s
VERY LOW START UP CURRENT: 150
A
s
UNDER VOLTAGE LOCKOUT WITH
HYSTERESIS
s
PROGRAMMABLE OSCILLATOR
FREQUENCY
s
DEAD TIME 1.25
s
s
dV/dt IMMUNITY UP TO
50V/ns
s
ESD PROTECTION
DESCRIPTION
The device is a high voltage half bridge driver with
built in oscillator. The frequency of the oscillator can
be programmed using external resistor and capaci-
tor. The internal circuitry of the device allows it to be
driven also by external logic signal.
The output drivers are designed to drive external n-
channel power MOSFET and IGBT. The internal log-
ic assures a dead time [typ. 1.25
s] to avoid cross-
conduction of the power devices.
Two version are available: L6569 and L6569A. They
differ in the low voltage gate driver start up sequence.
Minidip
SO8
ORDERING NUMBERS:
L6569
L6569D
L6569A
L6569AD
HIGH VOLTAGE HALF BRIDGE
DRIVER WITH OSCILLATOR
BLOCK DIAGRAM
R
F
C
F
LOGIC
BIAS
REGULATOR
COMP
COMP
LEVEL
SHIFTER
BUFFER
R
F
C
F
GND
HIGH
SIDE
DRIVER
LOW SIDE
DRIVER
HVG
LVG
OUT
BOOT
V
S
R
HV
C
VS
C
BOOT
H.V.
LOAD
D94IN058D
CHARGE
PUMP
Source
1
8
7
6
5
4
3
2
V
S
V
S
L6569 L6569A
2/13
ABSOLUTE MAXIMUM RATINGS
(*)The device has an internal zener clamp between GND and VS (typical 15.6V).Therefore the circuit should not be driven by a DC low im-
pedance power source.
Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 900 V (Human Body Model)
THERMAL DATA
RECOMMENDED OPERATING CONDITIONS
PIN CONNECTION
Symbol
Parameter
Value
Unit
I
S
(*)
Supply Current
25
mA
V
CF
Oscillator Resistor Voltage
18
V
V
LVG
Low Side Switch Gate Output
14.6
V
V
OUT
High Side Switch Source Output
-1 to V
BOOT
- 18
V
V
HVG
High Side Switch Gate Output
-1 to V
BOOT
V
V
BOOT
Floating Supply Voltage
618
V
V
BOOT/OUT
Floating Supply vs OUT Voltage
18
V
dV
BOOT
/dt
VBOOT Slew Rate (Repetitive)
50
V/ns
dV
OUT
/dt
VOUT Slew Rate (Repetitive)
50
V/ns
T
stg
Storage Temperature
-40 to 150
C
T
j
Junction Temperature
-40 to 150
C
T
amb
Ambient Temperature (Operative)
-40 to 125
C
Symbol
Parameter
Minidip
SO8
Unit
R
th j-amb
Thermal Resistance Junction-Ambient Max
100
150
C/W
Symbol
Parameter
Min.
Max.
Unit
V
S
Supply Voltage
10
V
CL
V
V
BOOT
Floating Supply Voltage
-
500
V
V
OUT
High Side Switch Source Output
-1
V
BOOT
-V
CL
V
f
out
Oscillation Frequency
200
kHz
V
S
R
F
C
F
GND
1
3
2
4
LVG
OUT
HVG
BOOT
8
7
6
5
D94IN059
3/13
L6569 L6569A
PIN FUNCTION
ELECTRICAL CHARACTERISTCS (V
S
= 12V; V
BOOT
- V
OUT
= 12V; T
j
= 25
C; unless otherwise specified.)
N
Pin
Description
1
VS
Supply input voltage with internal clamp [typ. 15.6V]
2
RF
Oscillator timing resistor pin.
A buffer set alternatively to V
S
and GND can provide current to the external resistor RF
connected between pin 2 and 3.
Alternatively, the signal on pin 2 can be used also to drive another IC (i.e. another L6569 to drive
a full H-bridge)
3
CF
Oscillator timing capacitor pin.
A capacitor connected between this pin and GND fixes (together with R
F
) the oscillating
frequency
Alternatively an external logic signal can be applied to the pin to drive the IC.
4
GND
Ground
5
LVG
Low side driver output.
The output stage can deliver 170mA source and 270mA sink [typ.values].
6
OUT
Upper driver floating reference
7
HVG
High side driver output.
The output stage can deliver 170mA source and 270mA sink [typ.values].
8
BOOT
Bootstrap voltage supply.
It is the upper driver floating supply. The bootstrap capacitor connected between this pin and pin
6 can be fed by an internal structure named "bootstrap driver" (a patented structure). This
structure can replace the external bootstrap diode.
Symbol
Pin
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
SUVP
1
VS Turn On Threshold
8.3
9
9.7
V
V
SUVN
VS Turn Off Threshold
7.3
8
8.7
V
V
SUVH
VS Hysteresis
0.7
1
1.3
V
V
CL
VS Clamping Voltage
I
S
= 5mA
14.6
15.6
16.6
V
I
SU
Start Up Current
V
S
< V
SUVN
150
250
A
I
q
Quiescent Current
V
S
> V
SUVP
500
700
A
I
BOOTLK
8
Leakage Current BOOT pin vs
GND
V
BOOT
= 580V
5
A
I
OUTLK
6
Leakage Current OUT pin vs
GND
V
OUT
= 562V
5
A
I
HVG SO
7
High Side Driver Source Current
V
HVG
= 6V
110
175
mA
I
HVG SI
High Side Driver Sink Current
V
HVG
= 6V
190
275
mA
I
LVG SO
5
Low Side Driver Source Current
V
LVG
= 6V
110
175
mA
I
LVG S
I
Low Side Driver Sink Current
V
LVG
= 6V
190
275
mA
L6569 L6569A
4/13
OSCILLATOR FREQUENCY
The frequency of the internal oscillator can be programmed using external resistor and capacitor.
The nominal oscillator frequency can be calculated using the following equation:
Where R
F
and C
F
are the external resistor and capacitor.
The device can be driven in "shut down" condition keeping the C
F
pin close to GND, but some cares have to be
taken:
1. When C
F
is to GND the high side driver is off and the low side is on
2. The forced discharge of the oscillator capacitor C
F
must not be shorter than 1us: a simple way to do this is to
limit the current discharge with a resistive path imposing R C
F
>1
s (see fig.1)
Figure 1.
V
RFO
N
2
RF High Level Output Voltage
I
RF
= 1mA
V
S
-0.05
V
S
-0.2
V
V
RF OFF
RF Low Level Output Voltage
I
RF
= -1mA
50
200
mV
V
CFU
3
CF Upper Threshold
7.7
8
8.2
V
V
CFL
CF Lower Threshold
3.80
4
4.3
V
t
d
Internal Dead Time
0.85
1.25
1.65
s
DC
Duty Cycle, Ratio Between Dead
Time + Conduction Time of High
Side and Low Side Drivers
0.45
0.5
0.55
R
ON
On resistance of Boostrap
LDMOS
120
V
BC
Boostrap Voltage before UVLO
V
S
= 8.2
2.5
3.6
V
I
AVE
1
Average Current from Vs
No Load, fs = 60KHz
1.2
1.5
mA
f
out
6
Oscillation Frequency
R
T
= 12K; C
T
= 1nF
57
60
63
kHz
Symbol
Pin
Parameter
Test Condition
Min.
Typ.
Max.
Unit
f
OS C
1
2 R
F
C
F
I n2
-----------------------------------------
1
1.3863 R
F
C
F
------------------------------------------
=
=
R
F
C
F
GND
M
1
2
3
4
8
7
6
5
fault signal
R
ELECTRICAL CHARACTERISTCS (continued)
5/13
L6569 L6569A
Bootstrap Function
The L6569 has an internal Bootstrap structure that enables the user to avoid the external diode needed, in sim-
ilar devices, to perform the charge of the bootstrap capacitor that, in turns, provide an appropriate driving to the
Upper External Mosfet.
The operation is achieved with an unique structure (patented) that uses a High Voltage Lateral DMOS driven
by an internal charge pump (see Block Diagram) and synchronized, with a 50 nsec delay, with the Low Side
Gate driver (LVG pin), actually working as a synchronous rectifier .
The charging path for the Bootstrap capacitor is closed via the Lower External Mosfet that is driven ON (i.e. LVG
High) for a time interval:
T
C
= R
F
C
F
In2
1.1 R
F
C
F
starting from the time the Supply Voltage V
S
has reached the Turn On Voltage (V
SUVP
= 9 V typical value).
After time T
1
(see waveform Diagram) the LDMOS that charges the Bootstrap Capacitor, is on with a R
ON
=120
(typical value).
In the L6569A a different start up procedure is followed (see waveform Diagram). The Lower External Mosfet is
drive OFF until V
S
has reached the Turn On Threshold (V
SUVPp
), then again the T
C
time interval starts as above.
Being the LDMOS used to implement the bootstrap operation a "bi-directional" switch the current flowing into
the BOOT pin (pin 8) can lead an undue stress to the LDMOS itself if a ZERO VOLTAGE SWITCHING opera-
tions is not ensured, and then an high voltage is applied to the BOOT pin. This condition can occur, for example,
when the load is removed and an high resistive value is placed in series with the gate of the external Power
Mos. To help the user to secure his design a SAFE OPERATING AREA for the Bootstrap LDMOS is provided
(fig. 7).
Let's consider the steps that should be taken.
1) Calculate the Turn on delay ( td ) of your Lower Power MOS:
2) Calculate the Fall time ( tf ) of your Lower Power MOS:
where:
R
g
= External gate resistor
R
id
= 50
, typical equivalent output resistance of the driving buffer (when sourcing current)
V
TH
, C
iss
and Q
gd
are Power MOS parameters
V
S
= Low Voltage Supply.
3) Sketch the VBOOT waveform (using log-log scales) starting from the Drain Voltage of the Lower Power MOS
(remember to add the Vs, your Low Voltage Supply, value) on the Bootstrap LDMOS SOA . On fig. 8 an example
is given where:
V
S
= Low Voltage Supply
V
HV
= High Voltage Supply Rail
The V
BOOT
voltage swing must fall below the curve identified by the actual operating frequency of your applica-
tion.
t
d
R
g
R
i d
+
(
)
C
i ss
1
1
V
T H
V
S
-----------
--------------------
ln
=
t
f
R
g
R
i d
+
V
S
V
T H
------------------------
Q
gd
=
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