L9380
TRIPLE HIGH-SIDE MOSFET DRIVER
OVERVOLTAGE CHARGE PUMP SHUT OFF
FOR V
VS
> 25V
REVERSE BATTERY PROTECTION (REFER-
RING TO THE APPLICATION CIRCUIT DIA-
GRAM)
PROGRAMMABLE OVERLOAD PROTEC-
TION FUNCTION FOR CHANNEL 1 AND 2
OPEN GROUND PROTECTION FUNCTION
FOR CHANNEL 1 AND 2
CONSTANT GATE CHARGE/DISCHARGE
CURRENT
DESCRIPTION
The L9380 device is a controller for three external
N-channel power MOS transistors in "High-Side
Switch" configuration. It is intended for relays re-
placement in automotive electric control units.
April 1998
T1
VS
N.C.
T2
PR
IN2
IN3
IN1
EN
G2
N.C.
S2
G1
S1
D2
N.C.
D1
CP
1
3
2
4
5
6
7
8
9
18
17
16
15
14
12
13
11
19
10
20
GND
G3
D98AT391
PIN CONNECTION (Top view)
SO20
ORDERING NUMBER: L9380
1/12
VS
GND
DRIVER 1
1
ENN
-
CHARGE PUMP
OVERVOLTAGE
CP
T1
VSI
IN1
+
1
VSI
T2
IN2
IN3
EN
CP
IPR
D1
S1
G1
DRIVER 2
1
ENN
-
VSI
+
1
VSI
CP
D2
S2
G2
IPR
ENN
1
VSI
CP
DRIVER 3
G3
ENN
VS
VSI
PR
I
PR
2V
REFERENCE
REG.
D98AT390
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
S
DC Supply Voltage
-0.3 to +27
V
V
S
Supply Voltage pulse (t
400ms)
45
V
V
S
/dt
Supply Voltage slope
-10 to +10
V/
s
V
IN,EN
Input / Enable Voltage
-0.3 to +7
V
V
T
Timer Voltage
-0.3 to 27
V
V
D, G, S
Drain, gate, source voltage
-15 to +27
V
V
D, G, S
Drain, gate, source voltage pulse (t
400ms)
45
V
I
D, G, S
Drain, gate, source current (t
2ms)
0 to +4
mA
T
j
Operating Junction Temperature
-40 to 150
C
T
stg
Storage Temperature
-65 to 150
C
Note: ESD for all pins, except the timer pins, are according to MIL 883C, tested at 2KV, corresponds to a maximum energy dissipation of 0.2mJ.
The timer pins are tested with 800V
L9380
2/12
THERMAL DATA
Symbol
Parameter
Value
Unit
R
th j-amb
Thermal Resistance Junction to Ambient
100
C/W
LIFETIME
Symbol
Parameter
Condition
Value
Unit
t
B
Useful life time
V
S
= 0V
20
years
t
b
Operating life time
V
S
= 7 to 18.5V
5000
hours
PIN FUNCTIONS
N.
Name
Function
1
T1
Timer capacitor; the capacitor defines the time for the channel 1 shut down, after overload of
the external MOS transistor has been detected.
2
V
S
Supply Voltage.
4
T2
Timer capacitor; the capacitor defines the time for the channel 2 shut down, after overload of
the external MOS transistor has been detected.
5
PR
Programming resistor for overload detetcion threshold; the resistor from this pin to ground
defines the drain pin current and the charging of the timer capacitor.
6
IN3
Input 3; equal to IN1.
7
IN2
Input 2; equal to IN1.
8
IN1
Input 1; logic signal applied to this pin controls the driver 1; this pin features a current source to
assure defined high status when the pin is open.
9
EN
Enable logic signal high on this pin enables all channels
10
GND
Ground
11
G3
Gate 3 driver output; current source from CP or ground
12
G2
Gate 2 driver output; current source from CP or ground
14
S2
Source 2 sense input; monitors the source voltage.
15
S1
Source 1 sense input; monitors the source voltage.
16
G1
Gate 1 driver output; current source from CP or ground
17
D2
Drain 2 sense input; a programmable input bias current defines the drop across the external
resistor R
D1
; this drop fixes the overload threshold of the external MOS.
19
D1
Drain 1 sense input; a programmable input bias current defines the drop across the external
resistor R
D1
; this drop fixes the overload threshold of the external MOS.
20
CP
Charge pump capacitor; a alternating current source at this pin charges the connected
capacitor C
CP
to a voltage 10V higher than VS; the charge stored in this capacitor is thanused
to charge all the three gates of the power MOS transistors.
3, 13, 18
NC
Not connected
L9380
3/12
FUNCTIONAL DESCRIPTION
The Triple High-Side Power-MOS Driver features
all necessary control and protection functions to
switch on three Power-MOS transistors operating
as High-Side switches in automotive electronic
control units. The key application field is relays re-
placement in systems where high current loads,
usually motors with nominal currents of about 40A
connected to ground, has to be switched.
A high signal at the EN pin enables all three
channels. With enable low gates are clamped to
ground. In this condition the gate sink current is
higher than the specified 3mA. An enable low sig-
nal makes also a reset of the timer.
A low signal at the inputs switch on the gates of
the external MOS. A short circuit at the input
leads to permanent activation of the concerned
channel. In this case the device can be disabled
with the enable pin. The charge pump loading is
not influenced due to the enable input.
An external N-channel MOS driver in high side
configuration needs a gate driving voltage higher
than V
S
. It is generated by means of a charge
pump with integrated charge transfer capacitors
and one external charge storage capacitor C
CP
.
The charge pump is dimensioned to load a ca-
ELECTRICAL CHARACTERISTICS (7V
V
S
18.5V; -40C
T
J
150C, unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
I
VS
Static Operating Supply Current
V
S
= 14V
2.5
mA
CHARGE PUMP
V
CP
Charge Pump Voltage Above V
S
8
17
V
t
CP
Charging Time
V
CP
= V
S
+ 8V C
CP
= 100pF
200
s
V
SCP off
Overvoltage Shut down
20
30
V
V
SCP hys
Overvoltage Shut down
Hysteresis
1)
50
200
1000
mV
f
CP
Charge Pump frequency
1)
100
250
400
KHz
GATE DRIVERS
I
GSo
Gate Source Current
V
G
= V
S
-5
-3
-1
mA
I
GSi
Gate Sink Current
V
G
0.8V
1
3
5
mA
DRAIN - SOURCE SENSING
V
PR
Bias Current Programming
voltage
10
A
I
PR
100
A; V
D
4V
1.8
2
2.2
V
I
D Leak
Drain pin leakage current
V
S
= 0V; V
D
=14V
0
5
A
I
D
Drain pin bias current
V
S
V
D
+ 1V; V
D
5V
0.9 I
PR
1.1 I
PR
I
Smax
Source pin input current
V
S
V
D
+ 1V; V
D
7V
10
60
A
V
HYST
Comparator Hysteresis
20
mV
TIMER
V
THi
Timer threshold high
4
4.4
4.8
V
V
TLo
Timer threshold low
0.3
0.4
0.5
V
I
T
Timer Current
IN = 5V; V
T
= 2V
IN = 0V; V
S
< V
D
;
V
D
5V; V
T
= 2V
0.4 I
PR
-0.6 I
PR
0.6 I
PR
-0.4 I
PR
INPUTS
V
LOW
Input Enable low voltage
-0.3
1
V
V
HIGH
Input Enable high voltage
3
7
V
V
INhys
Input Enable Hysteresis
(1)
50
200
500
mV
I
IN
Input source current
V
IN
3V
-30
-5
A
I
EN
Enable sink current
V
EN
1V
5
30
A
t
d
Transfer time IN/ENABLE
V
S
= 14V V
G
= V
S
; OPEN GATE
2.5
s
NOTE: Not measured guaranteed by design
Function is given for supply voltage down to 5.5V. Function means: The channels are controlled from the
inputs, some other parameters may exceed the limit. In this case the programming voltage and timer
threshold will be lower. This leads to a lower protection threshold and time.
L9380
4/12
pacitor C
CP
of 33nF in less than 20ms up to 8V
above V
S
. The value of C
CP
depends on the input
capacitance of the external MOS and the decay
of the charge pump voltage down to that value
where no significant influence on the application
occurs.
The necessary charging time for C
CP
has to be
respected in the sequence of the input control sig-
nals. As a consequence the lower gate to source
voltage can cause a higher drop across the
Power-MOS and get into overload condition. In
this case the overload protection timer will start.
After the protection time the concerned channel
will be switched off. Channel 3 is not equipped
with an overload protection. The same situation
can occur due to a discharge of the storage ca-
pacitor caused by the gate short to ground. The
gate driver that is supplied from the pin CP, which
is the charge pump output, has a sink and source
current capability of 3mA. For a short-circuit of the
load (source to ground) the L9380 has no gate to
source limitation. The gate source protection must
be done externally.
Channel 1 and 2 provide drain to source voltage
sensing possibility with programmable shut-off
delay when the activation threshold was ex-
ceeded. This threshold V
DSmin
is set by the exter-
nal resistor R
D
. The bias current flowing through
this resistor is determined by the programming re-
sistor R
PR
. This external resistor R
PR
defines also
the charge and discharge current of the timer ca-
pacitor C
CT
. The drain to source threshold V
DSmin
and the timer shut off delay time T
off
can be cal-
culated:
V
DS
min = V
PR
(R
D
/R
PR
)
T
off
= 4.4 C
T
R
PR
V
IN
V
G
V
S
V
T
4.4V
0.4V
V
DSmin
t
d
t
d
T
off
D98AT392
Figure 4. Timing Characteristic.
I
D
I
PR
+ I
Dmax
I
Smax
I
S
V
D
> V
S
V
S
> V
D
V
S
= V
D
I
PR
0
D98AT393
Figure 5. Drain, source input current.
L9380
5/12
In application which don't use the overload pro-
tection or if one channel is not used, the Timer pin
of this channel must be connected to ground and
the drain pin with a resistor to V
bat
.
The timing characteristic illustrates the function
and the meaning of V
DSmin
and T
off
(see figure 4).
The input current of the overload sense compara-
tor is specified as I
Smax
. The sum I
PR
+ I
Dmax
gen-
erates a drop across the external resistor R
D
if
the drain pin voltage is higher than the source pin
(see Fig. 5). In the switching point the comparator
input source pin currents are equal and the half of
the specified current I
Smax
. For an offset compen-
sation equal external resistors (R
D
= R
S
) at drain
and source pin are imperative. The drain sense
comparator, which detects the overload, has a
symmetrical hysteresis of 20mV (see Fig. 6). Ex-
ceeding the source pin voltage by 10mV with re-
spect to the drain voltage forces the timer capaci-
tor to discharge. Decreasing the source pin
voltage 10mV lower than the drain pin voltage an
overload of the external MOS is detected and the
timer capacitor will be loaded. After reaching a
voltage at pin CT higher than the timer threshold
V
Thi
the influenced channel is switched off. In this
case the overload is stored in the timer capacitor.
The timer capacitor will be discharged with a
'High' signal at the input (see Fig. 4). After reach-
ing the lower timer threshold V
TLo
the overload
protection is reset and the channel is able to
switch on again.
The application diagram is shown in Fig. 7. Be-
cause of the transients present at the power lines
during operation and possible disturbances in the
system the external resistors are necessary.
Positive ISO-Pulses at Drain, Gate Source are
clamped with an active clamping structure. The
clamping voltage is less than 60V. Negative
Pulses are only clamped with the ESD-Structure
less than -15V. This transients lower than -15V
can influence the other channels.
In order to protect the transistor against overload
and gate breakdown protection diodes between
gate and source and gate and drain has to be
connected. In case of overvoltage into V
S
(V
S
>
20V) the charge pump oscillation is stopped.
Then the charge pump capacitor will be loaded by
a diode and a resistor in series up to V
S
(see
Block Diagram). In this case the channels are not
influenced. In reverse battery condition the pins
D1, D2, S1, S2 follow the battery potential down
to -13V (high impedance) and the gate driver pins
G1, G2 is referred to S1, S2. In this way it is as-
sured that M1 and M2 will not be driven into the
linear conductive mode. This protection function
is operating for V
S1
, V
S2
down to -15V. The gate
driver output G3 is referred to the D1 in this case.
This function guarantees that the source to
source connected N-Channel MOS transistors M3
and M4 remains OFF.
All the supplies and the in- and output of the PC-
Board are supplied with a 40 wires flat cable (not
used wires are left open). This cable is submitted
to the RF in the strip-line like described in DIN
40839-4 or ISO 11456-5.
The measured circuit was build up on a PCB
board with ground plane. In the frequency range
from 1MHz to 400MHz and 80% AM-modulation
of 1KHz with field strength of 200V/m no influence
to the basic function was detected on a typical de-
vice. The failure criteria is an envelope of the out-
put signal with 20% in the amplitude and 2% in
the time.
V
T
-10mV
V
Dr
+10mV
V
So
D98AT394
Figure 6. Comparator hysteresis.
L9380
6/12
VS
GND
DRIVER 1
1
ENN
-
CHARGE PUMP
OVERVOLTAGE
CP
T1
VSI
IN1
+
1
VSI
T2
IN2
IN3
EN
CP
IPR
D1
S1
G1
DRIVER 2
1
ENN
-
VSI
+
1
VSI
CP
D2
S2
G2
IPR
ENN
1
VSI
CP
DRIVER 3
G3
ENN
VS
VSI
PR
I
PR
2V
REFERENCE
REG.
C1
D2
D1
C2
C3
C4
MICROCONTROLLER
LOAD CONTROL
M1
M2
R1
R2
R3
R4
R5
R6
D3
D4
D5
D6
R7
D7
M3
M4
D8
L4
L3
L2
L1
VALUE DRIVER
U405
M
M1
M
M2
D98AT395
V
BAT
R8
Figure 7. Application Circuit.
Recommendations to the application circuit: The timer and the charge capacitors are loaded with an al-
ternating current source. A short ground connection of the charge capacitor is indispensable to avoid
electromagnetic emigrations. The dimension of the resistors RD, RG and RS have to respect the maxi-
mum current during transients at each pin.
L9380
7/12
6
10
12
14
16
V
S
(V)
8
0
10
20
t
CH
(ms)
68nF
33nF
10nF
D98AT396
Figure 8. Charge Loading Time as function of V
S
(V
cp
= 8V +V
S
)
7
17
27
V
C
(V)
0
50
100
I
CP
(
A)
D98AT397
7V
10V
12V
16V
Figure 9. Charge Pump Current as function of
the Charge Voltage
-15
-10
-5
V
S
(V)
-1000
-800
-600
-400
-200
I
G
(
A)
D98AT398
Figure 10. Ground Loss Protection Gate Dis-
carge Current for Source Voltage
0
1
2
3
4
V
I
(V)
-20
-15
-10
-5
I
C
(
A)
D98AT399
Figure 11. Input Current as function of the Input
Voltage
24
24.5
25
25.5
V
S
(V)
20
30
V
CH
(V)
D98AT400
Figure 12. Overvoltage Shutdown of the Charge
Pump with Hysteresis
TYPICAL CHARACTERISTICS
Depending on production spread, certain deviations may occure. For limits (see pag. 4)
L9380
8/12
VS
GND
DRIVER 1
1
ENN
-
CHARGE PUMP
OVERVOLTAGE
CP
T1
VSI
IN1
+
1
VSI
T2
IN2
IN3
EN
CP
IPR
D1
S1
G1
DRIVER 2
1
ENN
-
VSI
+
1
VSI
CP
D2
S2
G2
IPR
ENN
1
VSI
CP
DRIVER 3
G3
ENN
VS
VSI
PR
I
PR
2V
REFERENCE
REG.
33
F
SMT_39A
SMB7W01-200
10nF
10nF
33nF
B60N06
10K
2K
2K
10K
2K
33V
18V
33V
18V
33V
18V
D98AT401
CAR-BATTERY
1K
1K
1K
100nF
5.6V
4.7nF
2.2nF
10K
2.2nF
10K
2.2nF
10K
2K
STD17N06
5
B60N06
5
B60N06
STD17N06
STD17N06
4.7nF
5.6V
3.125Hz
6.25Hz
12.5Hz
25Hz
f
2
4.7nF
5.6V
1K
4.7nF
PC-BOARD IN RF BOX
5.6V
10
9
8
7
2m
STRIPLINE
U(t)
f
2
f
2
1K
1K
1K
EN
IN3
IN2
6
IN1
2
V
S
1
V
BAT
2.2nF
2.2nF
2.2nF
2.2nF
OUT1
3
OUT2
4
OUT3
5
ANECHOIC CHAMBER
10K
20K
BNC
BNC
+
8
9
7
6
3
4
5
10
1
2
Figure 13. Measured Circuit.
The EMS of the device was verified in the below described setup.
L9380
9/12
Figure 14: PCB Board
Electromagnetic Emission Classification (EME)
Electromagnetic Emission classes presented below are typical data found on bench test. For detailes
test description please refer to "Electromagnetic Emission (EME) Measurement of Integrated Circuits,
DC to 1GHz" of VDE/ZVEI work group 767.13 and VDE/ZVEI work group 767.14 or IEC project number
47A 1967Ed. This data is targeted to board designers to allow an estimation of emission filtering effort
required in application. All measurements are done with the EMS-board (See pages 9, 10)
Pin
EME class
Remark
VCP
G
-
w
Electromagnetic Emission and Susceptivity is not tested in production.
L9380
10/12
SO20 PACKAGE MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.1
0.3
0.004
0.012
B
0.33
0.51
0.013
0.020
C
0.23
0.32
0.009
0.013
D
12.6
13
0.496
0.512
E
7.4
7.6
0.291
0.299
e
1.27
0.050
H
10
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.4
1.27
0.016
0.050
K
0 (min.)8 (max.)
1
10
11
20
A
e
B
D
E
L
K
H
A1
C
SO20MEC
h x 45
L9380
11/12
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-
THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1998 SGS-THOMSON Microelectronics Printed in Italy All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
L9380
12/12
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