1/20

March 2002

M24256-B
M24128-B

256/128 Kbit Serial I²C Bus EEPROM

With Three Chip Enable Lines

Compatible with I

C Extended Addressing

Two Wire I

C Serial Interface

Supports 400 kHz Protocol

Single Supply Voltage:

4.5V to 5.5V for M24xxx-B

2.5V to 3.6V for M24xxx-BV

2.5V to 5.5V for M24xxx-BW

1.8V to 3.6V for M24xxx-BS

1.8V to 5.5V for M24xxx-BR

Hardware Write Control

BYTE and PAGE WRITE (up to 64 Bytes)

RANDOM and SEQUENTIAL READ Modes

Self-Timed Programming Cycle

Automatic Address Incrementing

Enhanced ESD/Latch-Up Behavior

More than 100000 Erase/Write Cycles

More than 1 Million Erase/Write cycles for the

products specified in Table 13

More than 40 Year Data Retention

DESCRIPTION
These I

C-compatible electrically erasable

programmable memory (EEPROM) devices are
organized as 32K x 8 bits (M24256-B) and 16K x
8 bits (M24128-B).
These memory devices are compatible with the
I

C extended memory standard. This is a two wire

Figure 1. Logic Diagram

AI02809

SDA

VCC

M24256-B
M24128-B

SCL

VSS

E0-E2

Table 1. Signal Names

E0, E1, E2

Chip Enable

SDA

Serial Data

SCL

Serial Clock

Write Control

Supply Voltage

Ground

PDIP8 (BN)

0.25 mm frame

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

M24256-B, M24128-B

2/20

serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4-
bit unique Device Type Identifier code (1010) in
accordance with the I

C bus definition.

The memory behaves as a slave device in the I

protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory
inserts an acknowledge bit during the 9

bit time,

following the bus master's 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by

a STOP condition after an Ack for WRITE, and
after a NoAck for READ.
Power On Reset: V

Lock-Out Write Protect

In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until the V

voltage has reached

the POR threshold value, and all operations are
disabled the device will not respond to any
command. In the same way, when V

drops from

the operating voltage, below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable and
valid V

must be applied before applying any

logic signal.

Figure 2A. PDIP8 Connections

SDA

VSS

SCL

VCC

AI02810

M24256-B
M24128-B

Figure 2B. SO8 and TSSOP8 Connections

AI02811

SDA

VSS

SCL

VCC

M24256-B
M24128-B

Table 2. Absolute Maximum Ratings

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. IPC/JEDEC J-STD-020A
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500

, R2=500

)

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

40 to 125

°C

STG

Storage Temperature

65 to 150

°C

LEAD

Lead Temperature during Soldering

PDIP: 10 seconds

SO: 20 seconds (max)

TSSOP: 20 seconds (max)

260

235

°C

Input or Output range

-V voltage range
all other voltage ranges

0.6 to 4.2
0.6 to 6.5

Supply Voltage

-V voltage range
all other voltage ranges

0.3 to 4.2
0.3 to 6.5

ESD

Electrostatic Discharge Voltage (Human Body model)

3000

3/20

M24256-B, M24128-B

When the power supply is turned on, V

rises

from V

to V

(min), passing through a value V

in between. The -V and -S versions of the device,
the M24256-BV and M24256-BS, ignore all
instructions until a time delay of t

has elapsed

after the moment that V

rises above the V

threshold. However, the correct operation of the
device is not guaranteed if, by this time, V

is still

below V

(min).No instructions should be sent

until the later of:
t

after V

passed the V

threshold

passed the V

(min) level

These values are specified in Table 8.

SIGNAL DESCRIPTION
Serial Clock (SCL)

The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a
slower clock, the master must have an open drain
output, and a pull-up resistor must be connected
from the SCL line to V

. (Figure 3 indicates how

the value of the pull-up resistor can be calculated).
In most applications, though, this method of
synchronization is not employed, and so the pull-
up resistor is not necessary, provided that the
master has a push-pull (rather than open drain)
output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to
transfer data in or out of the memory. It is an open
drain output that may be wire-OR'ed with other
open drain or open collector signals on the bus. A
pull up resistor must be connected from the SDA
bus to V

. (Figure 3 indicates how the value of

the pull-up resistor can be calculated).

Chip Enable (E2, E1, E0)
These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code.
These inputs must be tied directly to V

or V

establish the device select code. When
unconnected, the E2, E1 and E0 inputs are
internally read as V

(see Table 7 and Table 9)

Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC=V

) or disable (WC=V

)

write instructions to the entire memory area. When
unconnected, the WC input is internally read as
V

, and write operations are allowed.

When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not
acknowledged.

Figure 3. Maximum R

Value versus Bus Capacitance (C

BUS

) for an I

C Bus

AI01665

VCC

CBUS

SDA

MASTER

SCL

CBUS

100

CBUS (pF)

Maximum RP value (k

)

1000

fc = 400kHz

fc = 100kHz

M24256-B, M24128-B

4/20

DEVICE OPERATION
The memory device supports the I

C protocol.

This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note

AN1001

. Any device that sends data on to the bus

is defined to be a transmitter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
device is always a slave device in all
communication.
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device
continuously monitors (except during an internal

Write cycle) the SDA and SCL lines for a START
condition, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates
communication between the memory device and
the bus master. A STOP condition at the end of a
Read command, after (and only after) a NoAck,
forces the memory device into its standby state. A
STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a
successful byte transfer. The bus transmitter,
whether it be master or slave, releases the SDA
bus after sending eight bits of data. During the 9

clock pulse period, the receiver pulls the SDA bus
low to acknowledge the receipt of the eight data
bits.

Figure 4. I

C Bus Protocol

SCL

SDA

SCL

SDA

START

Condition

SDA

Input

SDA

Change

AI00792B

STOP

Condition

MSB

ACK

START

Condition

SCL

MSB

ACK

STOP

Condition

5/20

M24256-B, M24128-B

Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high
transition, and the data must change

only

when

the SCL line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is
further subdivided into: a 4-bit Device Type
Identifier, and a 3-bit Chip Enable "Address" (E2,
E1, E0).

To address the memory array, the 4-bit Device
Type Identifier is 1010b.
Up to eight memory devices can be connected on
a single I

C bus. Each one is given a unique 3-bit

code on its Chip Enable inputs. When the Device
Select Code is received on the SDA bus, the
memory only responds if the Chip Select Code is
the same as the pattern applied to its Chip Enable
pins.

The 8

bit is the RW bit. This is set to `1' for read

and `0' for write operations. If a match occurs on
the Device Select Code, the corresponding
memory gives an acknowledgment on the SDA
bus during the 9

bit time. If the memory does not

match the Device Select Code, it deselects itself

from the bus, and goes into stand-by mode,
leaving Serial Data (SDA) in the high impedance
(NoACK) state.
There are several modes both for read and write.
These are summarized in Table 6 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte
(Table 4) is sent first, followed by the Least
significant Byte (Table 5). Bits b15 to b0 form the
address of the byte in memory. Bit b15 is treated
as a Don't Care bit on the M24256-B memory. Bits
b15 and b14 are treated as Don't Care bits on the
M24128-B memory.
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to '0', as
shown in Table 6. The memory acknowledges this,
and waits for two address bytes. The memory
responds to each address byte with an
acknowledge bit, and then waits for the data
byte(s).

Table 3. Device Select Code

Note: 1. The most significant bit, b7, is sent first.

Device Type Identifier

Chip Enable

Device Select Code

Table 4. Most Significant Byte

Note: 1. b15 is treated as Don't Care on the M24256-B series.

b15 and b14 are Don't Care on the M24128-B series.

Table 5. Least Significant Byte

b15

b14

b13

b12

b11

b10

Table 6. Operating Modes

Note: 1. X =

or V

Mode

RW bit

Data Bytes

Initial Sequence

Current Address Read

START, Device Select, RW = `1'

Random Address Read

START, Device Select, RW = `0', Address

reSTART, Device Select, RW = `1'

Sequential Read

Similar to Current or Random Address Read

Byte Write

START, Device Select, RW = `0'

Page Write

START, Device Select, RW = `0'

M24256-B, M24128-B

6/20

Figure 5. Write Mode Sequences with WC=1 (data write inhibited)

STOP

START

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

START

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

AI01120C

PAGE WRITE
(cont'd)

WC (cont'd)

STOP

DATA IN N

ACK

NO ACK

R/W

ACK

NO ACK

R/W

NO ACK

Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the two address bytes)
will not modify the memory contents, and the
accompanying data bytes will

not

acknowledged, as shown in Figure 5.
Byte Write
In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed location is write
protected by the WC pin, the memory replies with
a NoAck, and the location is not modified. If,

instead, the WC pin has been held at 0, as shown
in Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.

Page Write
The Page Write mode allows up to 64 bytes to be
written in a single write cycle, provided that they
are all located in the same 'row' in the memory:
that is the most significant memory address bits
(b14-b6 for the M24256-B and b13-b6 for the
M24128-B) are the same. If more bytes are sent
than will fit up to the end of the row, a condition
known as `roll-over' occurs. Data starts to become

7/20

M24256-B, M24128-B

Figure 6. Write Mode Sequences with WC=0 (data write enabled)

STOP

START

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

START

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

AI01106B

PAGE WRITE
(cont'd)

WC (cont'd)

STOP

DATA IN N

ACK

R/W

ACK

R/W

ACK

overwritten (in a way not formally specified in this
data sheet).
The master sends from one up to 64 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the
contents of the addressed memory location are
not modified, and each data byte is followed by a
NoAck. After each byte is transferred, the internal
byte address counter (the 6 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition
immediately after the Ack bit (in the "10

bit" time

slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not
trigger the internal write cycle.

During the internal write cycle, the SDA input is
disabled internally, and the device does not
respond to any requests.
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory
disconnects itself from the bus, and copies the
data from its internal latches to the memory cells.
The maximum write time (t

) is shown in Table

10A, but the typical time is shorter. To make use of

M24256-B, M24128-B

8/20

Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then,

without

sending a STOP condition, the

master sends another START condition, and
repeats the Device Select Code, with the RW bit
set to `1'. The memory acknowledges this, and
outputs the contents of the addressed byte. The
master must

not

acknowledge the byte output, and

terminates the transfer with a STOP condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read mode, following a START
condition, the master sends a Device Select Code
with the RW bit set to `1'. The memory
acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The master
terminates the transfer with a STOP condition, as

this, an Ack polling sequence can be used by the
master.
The sequence, as shown in Figure 7, is:
Initial condition: a Write is in progress.
Step 1: the master issues a START condition

followed by a Device Select Code (the first byte
of the new instruction).

Step 2: if the memory is busy with the internal

write cycle, no Ack will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it responds
with an Ack, indicating that the memory is ready
to receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).

Read Operations
Read operations are performed independently of
the state of the WC pin.

Figure 7. Write Cycle Polling Flowchart using ACK

WRITE Cycle

in Progress

AI01847C

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

ReSTART

STOP

DATA for the

WRITE Operation

DEVICE SELECT

with RW = 1

Send Address

and Receive ACK

First byte of instruction
with RW = 0 already
decoded by the device

YES

START

Condition

Continue the

WRITE Operation

Continue the

Random READ Operation

9/20

M24256-B, M24128-B

After the last memory address, the address
counter `rolls-over' and the memory continues to
output data from memory address 00h.
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9

bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.

shown in Figure 8,

without

acknowledging the byte

output.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master

does

acknowledge the data byte output in

this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must

not

acknowledge the last

byte output, and

must

generate a STOP condition.

The output data comes from consecutive
addresses, with the internal address counter
automatically incremented after each byte output.

Figure 8. Read Mode Sequences

Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1

and 4

bytes) must be identical.

START

DEV SEL *

BYTE ADDR

START

DEV SEL

DATA OUT 1

AI01105C

DATA OUT N

STOP

START

CURRENT
ADDRESS
READ

DEV SEL

DATA OUT

RANDOM
ADDRESS
READ

STOP

START

DEV SEL *

DATA OUT

SEQUENTIAL
CURRENT
READ

STOP

DATA OUT N

START

DEV SEL *

BYTE ADDR

SEQUENTIAL
RANDOM
READ

START

DEV SEL *

DATA OUT 1

STOP

ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

M24256-B, M24128-B

10/20

Table 7. DC Characteristics
(T

= 40 to 85 °C; over all specified voltage ranges)

Note: 1. This is preliminary data.

Table 8. Power-Up Timing and V

Threshold

= 40 to 85 °C)

Note: 1. These parameters are characterized only.

Symbol

Parameter

Test Condition

Min.

Max.

Input Leakage Current
(SCL, SDA)

= V

± 2

µA

Output Leakage Current

OUT

= V

CC,

SDA in Hi-Z

± 2

µA

Supply Current

=5V, f

=400kHz (rise/fall time < 30ns)

-V series: V

=2.7V, f

=400kHz (rise/fall time < 30ns)

-W series: V

=2.5V, f

=400kHz (rise/fall time < 30ns)

-S series: V

=1.8V, f

=400kHz (rise/fall time < 30ns)

0.5

-R series: V

=1.8V, f

=100kHz (rise/fall time < 30ns)

0.8

CC1

Supply Current
(Stand-by)

= V

, V

= 5 V

µA

-V series:

= V

, V

= 2.7 V

µA

-W series:

= V

, V

= 2.5 V

µA

-S, -R series:

= V

, V

= 1.8 V

µA

Input Low Voltage
(SCL, SDA)

0.3

0.3V

Input High Voltage
(SCL, SDA)

-V, -S series:

0.7V

+0.6

other series:

0.7V

Input Low Voltage
(E0-E2, WC)

0.3

0.5

Input High Voltage
(E0-E2, WC)

-V, -S series:

0.7V

+0.6

other series:

0.7V

Output Low
Voltage

= 3 mA, V

= 5 V

0.4

-V series:

= 2.1 mA, V

= 2.7 V

0.4

-W series:

= 2.1 mA, V

= 2.5 V

0.4

-S, -R series:

= 0.7 mA, V

= 1.8 V

0.2

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Time delay to Read or Write instruction

200

Threshold Voltage

1.4

1.6

11/20

M24256-B, M24128-B

Table 9. Input Parameters

= 25 °C, f = 400 kHz)

Note: 1. Sampled only, not 100% tested.

Table 10A. AC Characteristics

Note: 1. For a reSTART condition, or following a write cycle.

2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Input Capacitance (SDA)

Input Capacitance (other pins)

Input Impedance (E0-E2, WC)

0.5 V

Input Impedance (E0-E2, WC)

0.7V

500

Pulse width ignored
(Input Filter on SCL and SDA)

Single glitch

100

Symbol

Alt.

Parameter

M24xxx-B

M24xxx-BV

M24xxx-BW

Unit

=4.5 to 5.5 V

=40 to 85°C

=2.5 to 3.6 V

=40 to 85°C

=2.5 to 5.5 V

=40 to 85°C

Min

Max

Min

Max

Min

Max

CH1CH2

Clock Rise Time

300

CL1CL2

Clock Fall Time

300

DH1DH2

SDA Rise Time

300

DL1DL2

SDA Fall Time

300

CHDX

SU:STA

Clock High to Input Transition

600

CHCL

HIGH

Clock Pulse Width High

600

DLCL

HD:STA

Input Low to Clock Low (START)

600

CLDX

HD:DAT

Clock Low to Input Transition

CLCH

LOW

Clock Pulse Width Low

1300

DXCX

SU:DAT

Input Transition to Clock
Transition

100

CHDH

SU:STO

Clock High to Input High (STOP)

600

DHDL

BUF

Input High to Input Low (Bus
Free)

1300

CLQV

Clock Low to Data Out Valid

200

900

200

900

200

900

CLQX

Data Out Hold Time After Clock
Low

200

SCL

Clock Frequency

400

kHz

Write Time

M24256-B, M24128-B

12/20

Table 11A. AC Characteristics

Note: 1. For a reSTART condition, or following a write cycle.

2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This is preliminary data.

Symbol

Alt.

Parameter

M24xxx-BS

M24xxx-BR

Unit

=1.8 to 3.6 V

=40 to 85°C

=1.8 to 5.5 V

=40 to 85°C

Min

Max

Min

Max

CH1CH2

Clock Rise Time

300

1000

CL1CL2

Clock Fall Time

300

DH1DH2

SDA Rise Time

300

1000

DL1DL2

SDA Fall Time

300

CHDX

SU:STA

Clock High to Input Transition

600

4700

CHCL

HIGH

Clock Pulse Width High

600

4000

DLCL

HD:STA

Input Low to Clock Low (START)

600

4000

CLDX

HD:DAT

Clock Low to Input Transition

CLCH

LOW

Clock Pulse Width Low

1300

4700

DXCX

SU:DAT

Input Transition to Clock Transition

100

250

CHDH

SU:STO

Clock High to Input High (STOP)

600

4000

DHDL

BUF

Input High to Input Low (Bus Free)

1300

4700

CLQV

Clock Low to Data Out Valid

200

900

200

3500

CLQX

Data Out Hold Time After Clock Low

200

SCL

Clock Frequency

400

100

kHz

Write Time

Table 12. AC Measurement Conditions

Input Rise and Fall Times

50 ns

Input Pulse Voltages

0.2V

to 0.8V

Input and Output Timing
Reference Voltages

0.3V

to 0.7V

Figure 9. AC Testing Input Output Waveforms

AI00825

0.8VCC

0.2VCC

0.7VCC

0.3VCC

M24256-B, M24128-B

14/20

Table 13. Ordering Information Scheme

Note: 1. Available only on request (by preference, please use MN, SO8 150 mil width, package instead.

2. Available for the M24256-B only.
3. Available for the M24128-B only.
4. M24256-B and M24256-BW, produced with a process letter "V" on the top marking, guarantee more than 1 million Erase/Write cycle

endurance. For more information about these devices, and their device identification, please contact your nearest ST sales office,
and ask for the Product Change Notice PCEE0032.

Example:

M24256

Memory Capacity

Option

256

256 Kbit (32K x 8)

Tape and Reel Packing

128

128 Kbit (16K x 8)

Temperature Range

40 °C to 85 °C

Operating Voltage

Package

blank

4.5 V to 5.5 V (400 kHz)

PDIP8 (0.25 mm frame)

2.5 V to 3.6 V (400 kHz)

SO8 (150 mil width)

2.5 V to 5.5 V (400 kHz)

SO8 (200 mil width)

1.8 V to 3.6 V (400 kHz)

TSSOP8 (169 mil width)

1.8 V to 5.5 V (100 kHz)

TSSOP14 (169 mil width)

ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all 1s (FFh).
The notation used for the device number is as
shown in Table 13. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.

15/20

M24256-B, M24128-B

PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Outline

Note: 1. Drawing is not to scale.

PDIP-B

PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data

Symb.

inches

Typ.

Min.

Max.

Typ.

Min.

Max.

5.33

0.210

0.38

0.015

3.30

2.92

4.95

0.130

0.115

0.195

0.46

0.36

0.56

0.018

0.014

0.022

1.52

1.14

1.78

0.060

0.045

0.070

0.25

0.20

0.36

0.010

0.008

0.014

9.27

9.02

10.16

0.365

0.355

0.400

7.87

7.62

8.26

0.310

0.300

0.325

6.35

6.10

7.11

0.250

0.240

0.280

2.54

0.100

7.62

0.300

10.92

0.430

3.30

2.92

3.81

0.130

0.115

0.150

M24256-B, M24128-B

18/20

TSSOP8 8 lead Thin Shrink Small Outline

Note: 1. Drawing is not to scale.

TSSOP8-M

TSSOP8 8 lead Thin Shrink Small Outline

Symbol

inches

Typ.

Min.

Max.

Typ.

Min.

Max.

1.200

0.0472

0.050

0.150

0.0020

0.0059

1.000

0.800

1.050

0.0394

0.0315

0.0413

0.190

0.300

0.0075

0.0118

0.090

0.200

0.0035

0.0079

0.100

0.0039

3.000

2.900

3.100

0.1181

0.1142

0.1220

0.650

0.0256

6.400

6.200

6.600

0.2520

0.2441

0.2598

4.400

4.300

4.500

0.1732

0.1693

0.1772

0.600

0.450

0.750

0.0236

0.0177

0.0295

1.000

0.0394

0°

8°

0°

8°

19/20

M24256-B, M24128-B

Table 14. Revision History

Date

Rev.

Description of Revision

28-Dec-1999

2.1

TSSOP8 package added (pp 1, 2, OrderingInfo, PackageMechData).

24-Feb-2000

2.2

E2, E1, E0 must be tied to Vcc or Vss, on page 3
Low Pass Filter Time Constant changed to Glitch Filter in Table 8

22-Nov-2000

2.3

-V voltage range added

30-Jan-2001

2.4

-V voltage range changed to 2.5V to 3.6V
Lead Soldering Temperature in the Absolute Maximum Ratings table amended
Write Cycle Polling Flow Chart using ACK illustration updated
SO8(wide) package added
References to PSDIP8 changed to PDIP8, and Package Mechanical data updated

01-Jun-2001

2.5

-R voltage range added
Package mechanical data updated for TSSOP8 and TSSOP14 packages according to
JEDEC\MO-153
Document promoted from "Preliminary Data" to "Full Data Sheet"

16-Oct-2001

2.6

TSSOP14 package removed
Absolute Max Ratings and DC characteristics updated for M24256-BV

09-Nov-2001

2.7

Specification of Test Condition for Leakage Currents in the DC Characteristics table improved

21-Mar-2002

2.8

1 million Erase/Write cycle endurance guaranteed for certain products

M24256-B, M24128-B

20/20

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