M28F101
1 Mb (128K x 8, Chip Erase) FLASH MEMORY
April 1997
1/23
AI00666B
17
A0-A16
W
DQ0-DQ7
VPP
VCC
M28F101
G
E
VSS
8
Figure 1. Logic Diagram
5V
10% SUPPLY VOLTAGE
12V PROGRAMMING VOLTAGE
FAST ACCESS TIME: 70ns
BYTE PROGRAMING TIME: 10
s typical
ELECTRICAL CHIP ERASE in 1s RANGE
LOW POWER CONSUMPTION
Stand-by Current: 100
A max
10,000 ERASE/PROGRAM CYCLES
INTEGRATED ERASE/PROGRAM-STOP
TIMER
OTP COMPATIBLE PACKAGES and PINOUTS
ELECTRONIC SIGNATURE
Manufacturer Code: 20h
Device Code: 07h
DESCRIPTION
The M28F101 FLASH Memory is a non-volatile
memory which may be erased electrically at the
chip level and programmed byte-by-byte. It is or-
ganised as 128K bytes of 8 bits. It uses a command
register architecture to select the operating modes
and thus provides a simple microprocessor inter-
face. The M28F101 FLASH Memory is suitable for
applications where the memory has to be repro-
grammed in the equipment. The access time of
70ns makes the device suitable for use in high
speed microprocessor systems.
A0-A16
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
V
PP
Program Supply
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
PLCC32 (K)
32
1
PDIP32 (P)
TSOP32 (N)
8 x 20 mm
AI00668
NC
A13
A10
DQ5
17
A1
A0
DQ0
DQ1
DQ2
DQ3
DQ4
A7
A4
A3
A2
A6
A5
9
W
A8
1
A16
A9
DQ7
A12
A14
32
V
PP
V
CC
M28F101
A15
A11
DQ6
G
E
25
V
SS
Figure 2B. LCC Pin Connections
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
A14
A11
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
NC
W
A16
A12
VPP
VCC
A15
AI00667
M28F101
8
1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Figure 2A. DIP Pin Connections
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
A14
A11
G
E
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
NC
W
A16
A12
VPP
VCC
A15
AI00669B
M28F101
(Normal)
8
1
9
16
17
24
25
32
VSS
Figure 2C. TSOP Pin Connections
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
A14
A11
G
E
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
NC
W
A16
A12
VPP
VCC
A15
AI00670C
M28F101
(Reverse)
8
1
9
16
17
24
25
32
VSS
Figure 2D. TSOP Reverse Pin Connections
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Warning: NC = Not Connected.
2/23
M28F101
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
40 to 125
C
T
STG
Storage Temperature
65 to 150
C
V
IO
Input or Output Voltages
0.6 to 7
V
V
CC
Supply Voltage
0.6 to 7
V
V
A9
A9 Voltage
0.6 to 13.5
V
V
PP
Program Supply Voltage, during Erase
or Programming
0.6 to 14
V
Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above
those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.
Table 2. Absolute Maximum Ratings
DEVICE OPERATION
The M28F101 FLASH Memory employs a technol-
ogy similar to a 1 Megabit EPROM but adds to the
device functionality by providing electrical erasure
and programming. These functions are managed
by a command register. The functions that are
addressed via the command register depend on
the voltage applied to the V
PP
, program voltage,
input. When V
PP
is less than or equal to 6.5V, the
command register is disabled and M28F101 func-
tions as a read only memory providing operating
modes similar to an EPROM (Read, Output Dis-
able, Electronic Signature Read and Standby).
When V
PP
is raised to 12V the command regsiter
is enabled and this provides, in addition, Erase and
Program operations.
READ ONLY MODES, V
PP
6.5V
For all Read Only Modes, except Standby Mode,
the Write Enable input W should be High. In the
Standby Mode this input is don't care.
Read Mode. The M28F101 has two enable inputs,
E and G, both of which must be Low in order to
output data from the memory. The Chip Enable (E)
is the power control and should be used for device
selection. Output Enable (G) is the output control
and should be used to gate data on to the output,
independant of the device selection.
Standby Mode. In the Standby Mode the maxi-
mum supply current is reduced. The device is
placed in the Standby Mode by applying a High to
the Chip Enable (E) input. When in the Standby
Mode the outputs are in a high impedance state,
independant of the Output Enable (G) input.
Output Disable Mode. When the Output Enable
(G) is High the outputs are in a high impedance
state.
Electronic Signature Mode. This mode allows the
read out of two binary codes from the device which
identify the manufacturer and device type. This
mode is intended for use by programming equip-
ment to automatically select the correct erase and
programming algorithms. The Electronic Signature
Mode is active when a high voltage (11.5V to 13V)
is applied to address line A9 with E and G Low. With
A0 Low the output data is the manufacturer code,
when A0 is High the output is the device type code.
All other address lines should be maintained Low
while reading the codes. The electronic signature
may also be accessed in Read/Write modes.
READ/WRITE MODES, 11.4V
V
PP
12.6V
When V
PP
is High both read and write operations
may be performed. These are defined by the con-
tents of an internal command register. Commands
may be written to this register to set-up and exe-
cute, Erase, Erase Verify, Program, Program Verify
and Reset modes. Each of these modes needs 2
cycles. Eah mode starts with a write operation to
set-up the command, this is followed by either read
or write operations. The device expects the first
cycle to be a write operation and does not corrupt
data at any location in the memory. Read mode is
set-up with one cycle only and may be followed by
any number of read operations to output data.
Electronic Signature Read mode is set-up with one
cycle and followed by a read cycle to output the
manufacturer or device codes.
3/23
M28F101
Command
Cycles
1st Cycle
2nd Cycle
Operation
A0-A16
DQ0-DQ7
Operation
A0-A16
DQ0-DQ7
Read
1
Write
X
00h
Electronic
Signature
(2)
2
Write
X
90h
Read
00000h
20h
Read
00001h
07h
Setup Erase/
2
Write
X
20h
Erase
Write
X
20h
Erase Verify
2
Write
A0-A16
A0h
Read
X
Data Output
Setup Program/
2
Write
X
40h
Program
Write
A0-A16
Data Input
Program Verify
2
Write
X
C0h
Read
X
Data Output
Reset
2
Write
X
FFh
Write
X
FFh
Notes: 1. X = V
IL
or V
IH
.
2. Refer also to the Electronic Signature table.
Table 5. Commands
(1)
Identifier
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Hex Data
Manufacturer's Code
V
IL
0
0
1
0
0
0
0
0
20h
Device Code
V
IH
0
0
0
0
0
1
1
1
07h
Table 4. Electronic Signature
V
PP
Operation
E
G
W
A9
DQ0 - DQ7
Read Only
V
PPL
Read
V
IL
V
IL
V
IH
A9
Data Output
Output Disable
V
IL
V
IH
V
IH
X
Hi-Z
Standby
V
IH
X
X
X
Hi-Z
Electronic Signature
V
IL
V
IL
V
IH
V
ID
Codes
Read/Write
(2)
V
PPH
Read
V
IL
V
IL
V
IH
A9
Data Output
Write
V
IL
V
IH
V
IL
Pulse
A9
Data Input
Output Disable
V
IL
V
IH
V
IH
X
Hi-Z
Standby
V
IH
X
X
X
Hi-Z
Notes: 1. X = V
IL
or V
IH
.
2. Refer also to the Command table.
Table 3. Operations
(1)
4/23
M28F101
AI01275
3V
SRAM Interface
0V
1.5V
2.4V
EPROM Interface
0.45V
2.0V
0.8V
Figure 3. AC Testing Input Output Waveform
AI01276
1.3V
OUT
CL = 30pF or 100pF
CL = 30pF for SRAM Interface
CL = 100pF for EPROM Interface
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Figure 4. AC Testing Load Circuit
SRAM Interface Levels
EPROM Interface Levels
Input Rise and Fall Times
10ns
10ns
Input Pulse Voltages
0 to 3V
0.45V to 2.4V
Input and Output Timing Ref. Voltages
1.5V
0.8V and 2V
Table 6. AC Measurement Conditions
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
Note: 1. Sampled only, not 100% test.ed
Table 7. Capacitance
(1)
(T
A
= 25
C, f = 1 MHz )
A write to the command register is made by bringing
W Low while E is Low. The falling edge of W latches
Addresses, while the rising edge latches Data,
which are used for those commands that require
address inputs, command input or provide data
output.
The supply voltage V
CC
and the program voltage
V
PP
can be applied in any order. When the device
is powered up or when V
PP
is
6.5V the contents
of the command register defaults to 00h, thus
automatically setting-up Read operations. In addi-
tion a specific command may be used to set the
command register to 00h for reading the memory.
The system designer may chose to provide a con-
stant high V
PP
and use the register commands for
all operations, or to switch the V
PP
from low to high
only when needing to erase or program the mem-
ory. All command register access is inhibited when
V
CC
falls below the Erase/Write Lockout Voltage
(V
LKO
) of 2.5V.
If the device is deselected during Erasure, Pro-
gramming or Verification it will draw active supply
currents until the operations are terminated.
The device is protected against stress caused by
long erase or program times. If the end of Erase or
Programming operations are not terminated by a
Verify cycle within a maximum time permitted, an
internal stop timer automatically stops the opera-
tion. The device remains in an inactive state, ready
to start a Verify or Reset Mode operation.
READ/WRITE MODES (cont'd)
5/23
M28F101
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