1/22
April 2000
M48T129Y
M48T129V
3.3V-5V 1 Mbit (128Kb x8) TIMEKEEPER
SRAM
s
INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT, BATTERY AND CRYSTAL
s
YEAR 2000 COMPLIANT
s
BCD CODED CENTURY, YEAR, MONTH,
DAY, DATE, HOURS, MINUTES, and
SECONDS
s
BATTERY LOW WARNING FLAG
s
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s
TWO WRITE PROTECT VOLTAGES:
(V
PFD
= Power-fail Deselect Voltage)
M48T129Y: 4.2V
V
PFD
4.5V
M48T129V: 2.7V
V
PFD
3.0V
s
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
s
SOFTWARE CONTROLLED CLOCK
CALIBRATION for HIGH ACCURACY
APPLICATIONS
s
10 YEARS of DATA RETENTION and CLOCK
OPERATION in the ABSENCE of POWER
s
SELF CONTAINED BATTERY and CRYSTAL
in DIP PACKAGE
s
MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
s
PROGRAMMABLE ALARM OUTPUT ACTIVE
in BATTERY BACK-UP MODE
s
SURFACE MOUNT CHIP SET PACKAGING
INCLUDES a 44-PIN SOIC and a 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED
SEPARATELY)
s
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY and CRYSTAL
s
SNAPHAT
HOUSING (BATTERY/CRYSTAL)
IS REPLACEABLE
Figure 1. Logic Diagram
AI02260
17
A0-A16
DQ0-DQ7
VCC
M48T129Y
M48T129V
G
VSS
8
E
W
RST
IRQ/FT
32
1
SOH44
Surface Mount Chip Set Solution (CS)
SNAPHAT (SH)
Battery
PMDIP32 (PM)
Module
TSOP32
(8 x 20mm)
M48T129Y, M48T129V
2/22
Figure 2. DIP Connections
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
A15
A11
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A16
RST
VCC
AI02261
10
1
2
5
6
7
8
9
11
12
13
14
15
16
30
29
26
25
24
23
22
21
20
19
18
17
A12
A14
W
IRQ/FT
3
4
28
27
32
31
M48T129Y
M48T129V
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260
C for 10 seconds (total thermal budget not to exceed 150
C for longer than 30 seconds).
CAUTION: Negative undershoots below 0.3V are not allowed on any pin while in the Battery Back-up mode.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
C
T
STG
Storage Temperature (V
CC
Off, Oscillator Off)
40 to 85
C
V
IO
Input or Output Voltages
0.3 to V
CC
+0.3
V
V
CC
Supply Voltage
M48T129Y
0.3 to 7.0
V
M48T129V
0.3 to 4.6
V
I
O
Output Current
20
mA
P
D
Power Dissipation
1
W
For surface mount environments ST provides a
Chip Set solution consisting of a 44 pin 330mil
SOIC TIMEKEEPER Supervisor (M48T201V/Y)
and a 32 pin TSOP (8 x 20mm) LPSRAM
(M68Z128/W) packages.
The 44 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery.
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC pack-
age after the completion of the surface mount pro-
Table 1. Signal Names
A0-A16
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable Input
G
Output Enable Input
W
Write Enable Input
RST
Reset Output (open drain)
IRQ/FT
Interrupt / Frequency Test Output
(open drain)
V
CC
Supply Voltage
V
SS
Ground
DESCRIPTION
The M48T129Y/V TIMEKEEPER RAM is a 128Kb
x 8 non-volatile static RAM and real time clock,
with programmable alarms and a watchdog timer.
The special DIP package provides a fully integrat-
ed battery back-up memory and real time clock so-
lution. The M48T129Y/V directly replaces industry
standard 128Kb x 8 SRAM. It also provides the
non-volatility of Flash without any requirement for
special write timing or limitations on the number of
writes that can be performed.
3/22
M48T129Y, M48T129V
Figure 3. Block Diagram
AI02583
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VPFD
VCC
VSS
32,768 Hz
CRYSTAL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
16 x 8
TIMEKEEPER
REGISTERS
131,056 x 8
SRAM ARRAY
A0-A16
DQ0-DQ7
E
W
G
POWER
RST
IRQ/FT
cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SNAPHAT battery package is shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form. The part number is "M4Txx-BR12SH1".
The 32 pin 600 mil DIP Hybrid houses a controller
chip, SRAM, quartz crystal, and a long life lithium
button cell in a single package.
Figure 3 illustrates the static memory array and the
quartz controlled clock oscillator. The clock loca-
tions contain the century, year, month, date, day,
hour, minute, and second in 24 hour BCD format.
Corrections for 28, 29 (leap year), 30, and 31 day
months are made automatically. The nine clock
bytes (1FFFFh-1FFF9h and 1FFF1h) are not the
actual clock counters, they are memory locations
consisting of BiPORT
TM
read/write memory cells
within the static RAM array.
The M48T129Y/V includes a clock control circuit
which updates the clock bytes with current infor-
mation once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array. Byte
1FFF8h is the clock control register. This byte con-
trols user access to the clock information and also
stores the clock calibration setting.
Byte 1FFF7h contains the watchdog timer setting.
The watchdog timer can generate either a reset or
an interrupt, depending on the state of the Watch-
dog Steering bit (WDS). Bytes 1FFF6h-1FFF2h in-
clude bits that, when programmed, provide for
clock alarm functionality. Alarms are activated
when the register content matches the month,
date, hours, minutes, and seconds of the clock
registers. Byte 1FFF1h contains century informa-
tion. Byte 1FFF0h contains additional flag informa-
tion pertaining to the watchdog timer, the alarm
condition and the battery status. The M48T129Y/V
also has its own Power-Fail Detect circuit. This
control circuitry constantly monitors the supply
voltage for an out of tolerance condition. When
V
CC
is out of tolerance, the circuit write protects
the TIMEKEEPER register data and external
SRAM, providing data security in the midst of un-
predictable system operation. As V
CC
falls, the
control circuitry automatically switches to the bat-
tery, maintaining data and clock operation until
valid power is restored.
M48T129Y, M48T129V
4/22
Figure 4. Hardware Hookup for SMT Chip Set
(1)
Note: 1. For pin connections, see individual data sheets for M48T201Y/V and M68Z128/W at www.st.com.
2. For 5V, M48T129Y (M48T201Y + M68Z128). For 3.3V, M48T129V (M48T201V + M68Z128W).
3. SNAPHAT Top ordered separately.
AI03632
32,768 Hz
CRYSTAL
LITHIUM
CELL
A0-A16
DQ0-DQ7
E
VCC
W
G
WDI
RSTIN1
RSTIN2
VSS
E
W
G
VCC
VSS
A0-A16
DQ0-DQ7
0.1
F
0.1
F
5V
ECON
GCON
RST
IRQ/FT
SQW
M48T201Y/V
(2)
M68Z128/W
(2)
VOUT
SNAPHAT
(3)
BATTERY/CRYSTAL
READ MODE
The M48T129Y/V is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Ad-
dress Inputs defines which one of the 131,072
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within t
AVQV
(Ad-
dress Access Time) after the last address input
signal is stable, providing the E and G access
times are also satisfied. If the E and G access
times are not met, valid data will be available after
the latter of the Chip Enable Access Times (t
ELQV
)
or Output Enable Access Time (t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for t
AXQX
(Output
Data Hold Time) but will go indeterminate until the
next Address Access.
WRITE MODE
The M48T129Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are low
state after the address inputs are stable.
The start of a write is referenced from the latter oc-
curring falling edge of W or E. A write is terminated
by the earlier rising edge of W or E. The addresses
must be held valid throughout the cycle. E or W
must return high for a minimum of t
EHAX
from Chip
Enable or t
WHAX
from Write Enable prior to the ini-
tiation of another read or write cycle. Data-in must
be valid t
DVWH
prior to the end of write and remain
valid for t
WHDX
afterward. G should be kept high
during write cycles to avoid bus contention; al-
though, if the output bus has been activated by a
low on E and G a low on W will disable the outputs
t
WLQZ
after W falls.
5/22
M48T129Y, M48T129V
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Input Rise and Fall Times
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Figure 5. AC Testing Load Circuit
Note: Excluding open drain output pins
AI01803C
CL = 100pF
CL includes JIG capacitance
650
DEVICE
UNDER
TEST
1.75V
Table 3. Operating Modes
(1)
Note: 1. X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
2. See Table 7 for details.
Mode
V
CC
E
G
W
DQ0-DQ7
Power
Deselect
4.5V to 5.5V
or
3.0V to 3.6V
V
IH
X
X
High Z
Standby
Write
V
IL
X
V
IL
D
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
(2)
X
X
X
High Z
CMOS Standby
Deselect
V
SO
(2)
X
X
X
High Z
Battery Back-up Mode
external copies are independent of internal func-
tions except that they are updated periodically by
the simultaneous transfer of the incremented inter-
nal copy. TIMEKEEPER and Alarm Registers
store data in BCD.
DATA RETENTION MODE
With valid V
CC
applied, the M48T129Y/V operates
as a conventional BYTEWIDE
TM
static RAM.
Should the supply voltage decay, the RAM will au-
tomatically deselect, write protecting itself when
V
CC
falls between V
PFD
(max), V
PFD
(min) win-
dow. All outputs become high impedance and all
inputs are treated as "don't care".
Note: A power failure during a write cycle may cor-
rupt data at the current addressed location, but
does not jeopardize the rest of the RAM's content.
At voltages below V
PFD
(min), the memory will be
in a write protected state, provided the V
CC
fall
time is not less than t
F
. The M48T129Y/V may re-
spond to transient noise spikes on V
CC
that cross
into the deselect window during the time the de-
vice is sampling V
CC
. Therefore, decoupling of the
power supply lines is recommended.
When V
CC
drops below V
SO
, the control circuit
switches power to the internal battery, preserving
data and powering the clock. The internal energy
source will maintain data in the M48T129Y/V for
an accumulated period of at least 10 years at room
temperature. As system power rises above V
SO
,
the battery is disconnected, and the power supply
is switched to external V
CC
. Deselect continues for
t
REC
after V
CC
reaches V
PFD
(max). For a further
more detailed review of lifetime calculations,
please see Application Note AN1012.
TIMEKEEPER REGISTERS
The M48T129Y/V offers 16 internal registers
which contain TIMEKEEPER, Alarm, Watchdog,
Interrupt, Flag, and Control data. These registers
are memory locations which contain external (user
accessible) and internal copies of the data (usually
referred to as BiPORT TIMEKEEPER cells). The
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