1/18
February 2000
M48T35
M48T35Y
256 Kbit (32Kb x8) TIMEKEEPER
SRAM
s
INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
s
BYTEWIDETM RAM-LIKE CLOCK ACCESS
s
BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES and SECONDS
s
FREQUENCY TEST OUTPUT for REAL TIME
CLOCK
s
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
M48T35: 4.5V
V
PFD
4.75V
M48T35Y: 4.2V
V
PFD
4.5V
s
SELF-CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE
s
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT HOUSING
CONTAINING the BATTERY and CRYSTAL
s
SNAPHAT
HOUSING (BATTERY and
CRYSTAL) is REPLACEABLE
s
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 32Kb x8 SRAMs
Figure 1. Logic Diagram
AI01620B
15
A0-A14
W
DQ0-DQ7
VCC
M48T35
M48T35Y
G
VSS
8
E
Table 1. Signal Names
A0-A14
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
28
1
28
1
SOH28 (MH)
SNAPHAT (SH)
Battery
PCDIP28 (PC)
Battery CAPHAT
M48T35, M48T35Y
2/18
Figure 2A. DIP Connections
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
W
A11
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A12
A14
VCC
AI01621B
8
1
2
3
4
5
6
7
9
10
11
12
13
14
16
15
28
27
26
25
24
23
22
21
20
19
18
17
M48T35
M48T35Y
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below 0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
Grade 1
0 to 70
C
Grade 6
40 to 85
C
T
STG
Storage Temperature (V
CC
Off, Oscillator Off)
40 to 85
C
T
SLD
(2)
Lead Solder Temperature for 10 seconds
260
C
V
IO
Input or Output Voltages
0.3 to 7
V
V
CC
Supply Voltage
0.3 to 7
V
I
O
Output Current
20
mA
P
D
Power Dissipation
1
W
Figure 2B. SOIC Connections
AI01622B
8
2
3
4
5
6
7
9
10
11
12
13
14
22
21
20
19
18
17
16
15
28
27
26
25
24
23
1
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
W
A11
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A12
A14
VCC
M48T35Y
DESCRIPTION
The M48T35/35Y TIMEKEEPER
RAM is a 32Kb
x8 non-volatile static RAM and real time clock. The
monolithic chip is available in two special packag-
es to provide a highly integrated battery backed-up
memory and real time clock solution.
The M48T35/35Y is a non-volatile pin and function
equivalent to any JEDEC standard 32Kb x8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
write timing or limitations on the number of writes
that can be performed.
The 28 pin 600mil DIP CAPHAT houses the
M48T35/35Y silicon with a quartz crystal and a
long life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
3/18
M48T35, M48T35Y
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser-
tion of the SNAPHAT housing after reflow pre-
vents potential battery and crystal damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion. The SOIC and battery/crys-
tal packages are shipped separately in plastic anti-
static tubes or in Tape & Reel form.
For the 28 lead SOIC, the battery/crystal package
(i.e. SNAPHAT) part number is "M4T28-
BR12SH1".
As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T35/35Y are integrated on one silicon chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE clock information in the bytes with ad-
dresses 7FF8h-7FFFh.
Table 3. Operating Modes
(1)
Note: 1. X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
2. See Table 7 for details.
Mode
V
CC
E
G
W
DQ0-DQ7
Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
V
IH
X
X
High Z
Standby
Write
V
IL
X
V
IL
D
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
(2)
X
X
X
High Z
CMOS Standby
Deselect
V
SO
X
X
X
High Z
Battery Back-up Mode
Figure 3. Block Diagram
AI01623
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VPFD
VCC
VSS
32,768 Hz
CRYSTAL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
8 x 8 BiPORT
SRAM ARRAY
32,760 x 8
SRAM ARRAY
A0-A14
DQ0-DQ7
E
W
G
POWER
M48T35, M48T35Y
4/18
The clock locations contain the year, month, date,
day, hour, minute, and second in 24 hour BCD for-
mat. Corrections for 28, 29 (leap year), 30, and 31
day months are made automatically. Byte 7FF8h
is the clock control register. This byte controls user
access to the clock information and also stores the
clock calibration setting.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT read/write memory cells.
The M48T35/35Y includes a clock control circuit
which updates the clock bytes with current infor-
mation once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array.
The M48T35/35Y also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
tors the single 5V supply for an out of tolerance
condition. When V
CC
is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V
CC
. As V
CC
falls
below approximately 3V, the control circuitry con-
nects the battery which maintains data and clock
operation until valid power returns.
READ MODE
The M48T35/35Y is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 15 Ad-
dress Inputs defines which one of the 32,768 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
time (t
AVQV
) after the last address input signal is
stable, providing that the E and G access times
are also satisfied.
If the E and G access times are not met, valid data
will be available after the latter of the Chip Enable
Access time (t
ELQV
) or Output Enable Access time
(t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
.
If the Address Inputs are changed while E and G
remain active, output data will remain valid for Out-
put Data Hold time (t
AXQX
) but will go indetermi-
nate until the next Address Access.
WRITE MODE
The M48T35/35Y is in the Write Mode whenever
W and E are low. The start of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
of t
EHAX
from Chip Enable or t
WHAX
from Write En-
able prior to the initiation of another read or write
cycle. Data-in must be valid t
DVWH
prior to the end
of write and remain valid for t
WHDX
afterward. G
should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G, a low on W
will disable the outputs t
WLQZ
after W falls.
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Input Rise and Fall Times
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Figure 4. AC Testing Load Circuit
AI01030
5V
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
1.9k
DEVICE
UNDER
TEST
1k
5/18
M48T35, M48T35Y
Table 5. Capacitance
(1, 2)
(T
A
= 25 C)
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6. DC Characteristics
(T
A
= 0 to 70 C or 40 to 85 C; V
CC
= 4.75V to 5.5V or 4.5V to 5.5V)
Note: 1. Outputs deselected.
2. Negative spikes of 1V allowed for up to 10ns once per cycle.
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(T
A
= 0 to 70 C or 40 to 85 C)
Note: 1. All voltages referenced to V
SS
.
2. CAPHAT and M4T32-BR12SH1 SNAPHAT only, M4T28-BR12SH1 SNAPHAT top t
DR
= 7 years (typ).
3. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - grade 6 device).
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
10
pF
C
IO
(3)
Input / Output Capacitance
V
OUT
= 0V
10
pF
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
(1)
Input Leakage Current
0V
V
IN
V
CC
1
A
I
LO
(1)
Output Leakage Current
0V
V
OUT
V
CC
5
A
I
CC
Supply Current
Outputs open
50
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
3
mA
I
CC2
Supply Current (Standby) CMOS
E = V
CC
0.2V
3
mA
V
IL
(2)
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2.2
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage
I
OH
= 1mA
2.4
V
Symbol
Parameter
Min
Typ
Max
Unit
V
PFD
Power-fail Deselect Voltage
M48T35
4.5
4.6
4.75
V
M48T35Y
4.2
4.35
4.5
V
V
SO
Battery Back-up Switchover Voltage
3.0
V
t
DR
Expected Data Retention Time
(at 25C)
Grade 1
10
(2)
YEARS
Grade 6
10
(3)
YEARS
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