M48T58
M48T58Y
64 Kbit (8Kb x8) TIMEKEEPER
SRAM
July 1999
1/17
INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
BYTEWIDE
TM
RAM-LIKE CLOCK ACCESS
BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES and SECONDS
FREQUENCY TEST OUTPUT for REAL TIME
CLOCK
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
M48T58: 4.5V
V
PFD
4.75V
M48T58Y: 4.2V
V
PFD
4.5V
SELF-CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE
PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT
TOP
(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 8K x 8 SRAMs
DESCRIPTION
The M48T58/58Y TIMEKEEPER
RAM is an 8K x
8 non-volatile static RAM and real time clock. The
monolithic chip is available in two special packages
to provide a highly integrated battery backed-up
memory and real time clock solution.
AI01374B
13
A0-A12
W
DQ0-DQ7
VCC
M48T58
M48T58Y
G
E2
VSS
8
E1
FT
Figure 1. Logic Diagram
A0-A12
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
FT
Frequency Test Output (Open Drain)
E1
Chip Enable 1
E2
Chip Enable 2
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
28
1
PCDIP28 (PC)
Battery/Crystal
CAPHAT
SNAPHAT (SH)
Battery/Crystal
28
1
SOH28 (MH)
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
C
T
STG
Storage Temperature (V
CC
Off, Oscillator Off)
40 to 85
C
T
SLD
(2)
Lead Solder Temperature for 10 seconds
260
C
V
IO
Input or Output Voltages
0.3 to 7
V
V
CC
Supply Voltage
0.3 to 7
V
I
O
Output Current
20
mA
P
D
Power Dissipation
1
W
Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260
C for 10 seconds (total thermal budget not to exceed 150
C for longer than 30 seconds).
CAUTION: Negative undershoots below 0.3 volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 2. Absolute Maximum Ratings
(1)
Mode
V
CC
E1
E2
G
W
DQ0-DQ7
Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
V
IH
X
X
X
High Z
Standby
Deselect
X
V
IL
X
X
High Z
Standby
Write
V
IL
V
IH
X
V
IL
D
IN
Active
Read
V
IL
V
IH
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
(2)
X
X
X
X
High Z
CMOS Standby
Deselect
V
SO
X
X
X
X
High Z
Battery Back-up Mode
Notes: 1. X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
2. See Table 7 for details.
Table 3. Operating Modes
(1)
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
E2
A10
A8
A9
DQ7
W
A11
G
E1
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A12
FT
VCC
AI01375B
M48T58
M48T58Y
8
1
2
3
4
5
6
7
9
10
11
12
13
14
16
15
28
27
26
25
24
23
22
21
20
19
18
17
Figure 2A. DIP Pin Connections
AI01376B
8
2
3
4
5
6
7
9
10
11
12
13
14
22
21
20
19
18
17
16
15
28
27
26
25
24
23
1
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
E2
A10
A8
A9
DQ7
W
A11
G
E1
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A12
FT
VCC
M48T58Y
Figure 2B. SOIC Pin Connections
2/17
M48T58, M48T58Y
AI01030
5V
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
1.9k
DEVICE
UNDER
TEST
1k
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 4. AC Measurement Conditions
AI01377C
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VPFD
FT
VCC
VSS
32,768 Hz
CRYSTAL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
8 x 8 BiPORT
SRAM ARRAY
8184 x 8
SRAM ARRAY
A0-A12
DQ0-DQ7
E1
E2
W
G
POWER
Figure 3. Block Diagram
The M48T58/58Y is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The 28 pin 600mil DIP CAPHAT
TM
houses the
M48T58/58Y silicon with a quartz crystal and a long
life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery and crystal. The unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery and
crystal damage due to the high temperatures re-
quired for device surface-mounting. The SNAPHAT
housing is keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form.
DESCRIPTION (cont'd)
3/17
M48T58, M48T58Y
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
(1)
Input Leakage Current
0V
V
IN
V
CC
1
A
I
LO
(1)
Output Leakage Current
0V
V
OUT
V
CC
5
A
I
CC
Supply Current
Outputs open
50
mA
I
CC1
Supply Current (Standby) TTL
E1 = V
IH
, E2 = V
IL
3
mA
I
CC2
Supply Current (Standby) CMOS
E1 = V
CC
0.2V,
E2 = V
SS
+ 0.2V
3
mA
V
IL
(2)
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2.2
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
Output Low Voltage (FT)
(3)
I
OL
= 10mA
0.4
V
V
OH
Output High Voltage
I
OH
= 1mA
2.4
V
Notes: 1. Outputs Deselected.
2. Negative spikes of 1V allowed for up to 10ns once per Cycle.
3. The FT pin is Open Drain.
Table 6. DC Characteristics
(T
A
= 0 to 70
C; V
CC
= 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
10
pF
C
IO
(3)
Input / Output Capacitance
V
OUT
= 0V
10
pF
Notes: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected
Table 5. Capacitance
(1, 2)
(T
A
= 25
C, f = 1 MHz )
Symbol
Parameter
Min
Typ
Max
Unit
V
PFD
Power-fail Deselect Voltage (M48T58)
4.5
4.6
4.75
V
V
PFD
Power-fail Deselect Voltage (M48T58Y)
4.2
4.35
4.5
V
V
SO
Battery Back-up Switchover Voltage
3.0
V
t
DR
(2)
Expected Data Retention Time
7
YEARS
Notes: 1. All voltages referenced to V
SS
.
2. At 25C
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(T
A
= 0 to 70
C)
For the 28 lead SOIC, the battery/crystal package
( i.e. SNA PHAT ) p art num ber is "M 4T28-
BR12SH1".
As Figure 3 shows, the static memory array and the
q ua r t z c o nt r ol led c loc k o sc i lla t or of t h e
M48T58/58Y are integrated on one silicon chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE
TM
clock information in the bytes with
addresses 1FF8h-1FFFh. The clock locations con-
tain the year, month, date, day, hour, minute, and
second in 24 hour BCD format. Corrections for 28,
29 (leap year), 30, and 31 day months are made
automatically. Byte 1FF8h is the clock control reg-
ister. This byte controls user access to the clock
information and also stores the clock calibration
setting.
DESCRIPTION (cont'd)
4/17
M48T58, M48T58Y
Symbol
Parameter
Min
Max
Unit
t
PD
E1 or W at V
IH
or E2 at V
IL
before Power Down
0
s
t
F
(1)
V
PFD
(max) to V
PFD
(min) V
CC
Fall Time
300
s
t
FB
(2)
V
PFD
(min) to V
SO
V
CC
Fall Time
10
s
t
R
V
PFD
(min) to V
PFD
(max) V
CC
Rise Time
10
s
t
RB
V
SO
to V
PFD
(min) V
CC
Rise Time
1
s
t
REC
V
PFD
(max) to Inputs Recognized
40
200
ms
Notes: 1. V
PFD
(max) to V
PFD
(min) fall time of less than t
F
may result in deselection/write protection not occurring until 200
s after
V
CC
passes V
PFD
(min).
2. V
PFD
(min) to V
SO
fall time of less than t
FB
may cause corruption of RAM data.
Table 8. Power Down/Up Mode AC Characteristics
(T
A
= 0 to 70
C)
AI01168C
VCC
INPUTS
(PER CONTROL INPUT)
OUTPUTS
DON'T CARE
HIGH-Z
tF
tFB
tR
tPD
tRB
tDR
VALID
VALID
(PER CONTROL INPUT)
RECOGNIZED
RECOGNIZED
VPFD (max)
VPFD (min)
VSO
tREC
Figure 5. Power Down/Up Mode AC Waveforms
5/17
M48T58, M48T58Y
PDF 
ZIP