1/23
May 2000
M48T86
5V PC REAL TIME CLOCK
s
DROP-IN REPLACEMENT for PC
COMPUTER CLOCK/CALENDAR
s
COUNTS SECONDS, MINUTES, HOURS,
DAYS, DAY of the WEEK, DATE, MONTH and
YEAR with LEAP YEAR COMPENSATION
s
INTERFACED WITH SOFTWARE AS 128
RAM LOCATIONS:
14 Bytes of Clock and Control Registers
114 Bytes of General Purpose RAM
s
SELECTABLE BUS TIMING (Intel/Motorola)
s
THREE INTERRUPTS are SEPARATELY
SOFTWARE-MASKABLE and TESTABLE
Time-of-Day Alarm (Once/Second to
Once/Day)
Periodic Rates from 122s to 500ms
End-of-Clock Update Cycle
s
PROGRAMMABLE SQUARE WAVE OUTPUT
s
SELF-CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE
s
PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT
TOP
(to be Ordered Separately)
s
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP
CONTAINS the BATTERY and CRYSTAL
s
PIN and FUNCTION COMPATIBLE with
bq3285/7A and DS128887
Figure 1. Logic Diagram
AI01640
E
VCC
M48T86
RCL
RST
VSS
8
AD0-AD7
MOT
R/W
DS
AS
IRQ
SQW
28
1
24
1
SOH28 (MH)
SNAPHAT (SH)
Battery/Crystal
PCDIP24 (PC)
Battery/Crystal
CAPHAT
M48T86
2/23
Figure 2. DIP Connections
AD4
AD5
AD6
NC
AD1
AD2
AD3
NC
AD0
SQW
RST
NC
RCL
NC
NC
IRQ
DS
AS
AD7
VSS
E
R/W
MOT
VCC
AI01641
M48T86
8
1
2
3
4
5
6
7
9
10
11
12
13
14
16
15
24
23
22
21
20
19
18
17
Figure 3. SOIC Connections
AI01642
8
2
3
4
5
6
7
9
10
11
12
13
14
22
21
20
19
18
17
16
15
24
23
1
AD4
AD5
AD6
NC
AD1
AD2
AD3
AD0
SQW
RST
NC
RCL
NC
NC
IRQ
DS
AS
AD7
VSS
E
R/W
MOT
VCC
M48T86
NC
NC
NC
NC
26
25
28
27
VSS
Table 1. Signal Names
AD0-AD7
Multiplexed Address/Data Bus
E
Chip Enable Input
R/W
Write Enable Input
DS
Data Strobe Input
AS
Address Strobe Input
RST
Reset Input
RCL
RAM Clear Input
MOT
Bus Type Select Input
SQW
Square Wave Output
IRQ
Interrupt Request Output
V
CC
Supply Voltage
V
SS
Ground
NC
Not Connected Internally
DESCRIPTION
The M48T86 is an industry standard real time
clock (RTC).The M48T86 is composed of a lithium
energy source, quartz crystal, write-protection cir-
cuitry, and a 128 byte RAM array. This provides
the user with a complete subsystem packaged in
either a 24-pin DIP CAPHAT or 28-pin SNAPHAT
SOIC. Functions available to the user include a
non-volatile time-of-day clock, alarm interrupts, a
one-hundred-year clock with programmable inter-
rupts, square wave output, and 128 bytes of non-
volatile static RAM.
The 24 pin 600mil DIP CAPHATTM houses the
M48T86 silicon with a quartz crystal and a long life
lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is keyed
to prevent reverse insertion.
The SOIC and battery packages are shipped sep-
arately in plastic anti-static tubes or in Tape & Reel
form.
3/23
M48T86
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below 0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
C
T
STG
Storage Temperature (V
CC
Off, Oscillator Off)
40 to 85
C
T
SLD
(2)
Lead Solder Temperature for 10 seconds
260
C
V
IO
Input or Output Voltages
0.3 to 7.0
V
V
CC
Supply Voltage
0.3 to 7.0
V
P
D
Power Dissipation
1
W
For the 28 lead SOIC, the battery/crystal package
part number is "M4T28-BR12SH1".
Automatic deselection of the device provides in-
surance that data integrity is not compromised
should V
CC
fall below specified Power-fail Dese-
lect Voltage (V
PFD
) levels. The automatic deselec-
tion of the device remains in effect upon power up
for a period of 200ms (max) after V
CC
rises above
V
PFD
, provided that the Real Time Clock is running
and the count down chain is not reset. This allows
sufficient time for V
CC
to stabilize and gives the
system clock a wake up period so that a valid sys-
tem reset can be established.
The block diagram in Figure 3 shows the pin con-
nections and the major internal functions of the
M48T86.
SIGNAL DESCRIPTION
V
CC
, V
SS
. DC power is provided to the device on
these pins.The M48T86 utilizes a 5V V
CC
.
SQW (Square Wave Output). During normal op-
eration (i.e. valid V
CC
), the SQW pin can output a
signal from one of 13 taps.The frequency of the
SQW pin can be changed by programming Regis-
ter A as shown in Table 10. The SQW signal can
be turned on and off using the SQWE bit (Register
B; bit 3). The SQW signal is not available when
V
CC
is less than V
PFD
.
AD0-AD7 (Multiplexed Bi-Directional Address/
Data Bus). The M48T86 provides a multiplexed
bus in which address and data information share
the same signal path. The bus cycle consists of
two stages; first the address is latched, followed by
the data. Address/Data multiplexing does not slow
the access time of the M48T86, since the bus
change from address to data occurs during the in-
ternal RAM access time. Addresses must be valid
prior to the falling edge of AS, at which time the
M48T86 latches the address present on AD0-
AD7. Valid write data must be present and held
stable during the latter portion of the R/W pulse. In
a read cycle, the M48T86 outputs 8 bits of data
during the latter portion of the DS pulse. The read
cycle is terminated and the bus returns to a high
impedance state upon a high transition on R/W.
AS (Address Strobe Input). A positive going
pulse on the Address Strobe (AS) input serves to
demultiplex the bus. The falling edge of AS causes
the address present on AD0-AD7 to be latched
within the M48T86.
MOT (Mode Select). The MOT pin offers the flex-
ibility to choose between two bus types. When
connected to V
CC
, Motorola bus timing is selected.
When connected to V
SS
or left disconnected, Intel
bus timing is selected. The pin has an internal pull-
down resistance of approximately 20K ohms.
M48T86
4/23
DS (Data Strobe Input). The DS pin is also re-
ferred to as Read (RD). A falling edge transition on
the Data Strobe (DS) input enables the output dur-
ing a a read cycle. This is very similar to an Output
Enable (G) signal on other memory devices.
E (Chip Enable Input). The Chip Enable pin
must be asserted low for a bus cycle in the
M48T86 to be accessed. Bus cycles which take
place without asserting E will latch the addresses
present, but no data access will occur.
Figure 4. Block Diagram
AI01643
OSCILLATOR
BCD/BINARY
INCREMENT
E
/ 8
/ 64
/ 64
PERIODIC INTERRUPT/SQUARE WAVE SELECTOR
SQUARE WAVE
OUTPUT
POWER
SWITCH
AND
WRITE
PROTECT
AD0-AD7
REGISTERS A,B,C,D
CLOCK CALENDAR,
AND ALARM RAM
STORAGE
REGISTERS
(114 BYTES)
CLOCK/
CALENDAR
UPDATE
BUS
INTERFACE
VCC
VBAT
VCC
POK
DS
R/W
AS
SQW
RST
IRQ
DOUBLE
BUFFERED
RCL
IRQ (Interrupt Request Output). The IRQ pin is
an open drain output that can be used as an inter-
rupt input to a processor. The IRQ output remains
low as long as the status bit causing the interrupt
is present and the corresponding interrupt-enable
bit is set. IRQ returns to a high impedance state
whenever Register C is read. The RST pin can
also be used to clear pending interrupts. Because
the IRQ bus is an open drain output, it requires an
external pull-up resistor to V
CC
.
5/23
M48T86
RST (Reset Input). The M48T86 is reset when
the RST input is pulled low. With a valid V
CC
ap-
plied and a low on RST, the following events oc-
cur:
1. Periodic Interrupt Enable (PIE) bit is cleared to
a zero. (Register B; Bit 6)
2. Alarm Interrupt Enable (AIE) bit is cleared to a
zero.(Register B; bit 5)
3. Update Ended Interrupt Request (UF) bit is
cleared to a zero. (Register C; Bit 4)
4. Interrupt Request (IRQF) bit is cleared to a zero.
(Register C Bit 7)
5. Periodic Interrupt Flag (PF) bit is cleared to a
zero. (Register C; Bit 6)
6. The device is not accessible until RST is re-
turned high.
7. Alarm Interrupt Flag (AF) bit is cleared to a zero.
(Register C; Bit 5)
8. The IRQ pin is in the high impedance state.
9. Square Wave Output Enable (SQWE) bit is
cleared to zero. (Register B; Bit 3).
10.Update Ended Interrupt Enable (UIE) is cleared
to a zero. (Register B; Bit 4)
RCL (RAM Clear). The RCL pin is used to clear
all 114 storage bytes, excluding clock and control
registers, of the array to FF(hex) value. The array
will be cleared when the RCL pin is held low for at
least 100ms with the oscillator running. Usage of
this pin does not affect battery load. This function
is applicable only when V
CC
is applied.
R/W (Read/Write Input). The R/W pin is utilized
to latch data into the M48T86 and provides func-
tionality similar to W in other memory systems.
ADDRESS MAP
The address map of the M48T86 is shown in Fig-
ure 9. It consists of 114 bytes of user RAM, 10
bytes of RAM that contain the RTC time, calendar
and alarm data, and 4 bytes which are used for
control and status. All bytes can be read or written
to except for the following:
1. Registers C & D are read-only.
2. Bit 7 of Register A is read-only.
The contents of the four Registers A, B, C, and D
are described in the "Registers" section.
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