M48Z02
M48Z12
16 Kbit (2Kb x 8) ZEROPOWER
SRAM
May 1999
1/12
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
M48Z02: 4.50V
V
PFD
4.75V
M48Z12: 4.20V
V
PFD
4.50V
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 2K x 8 SRAMs
DESCRIPTION
The M48Z02/12 ZEROPOWER
RAM is a 2K x 8
non-volatile static RAM which is pin and functional
compatible with the DS1220.
A special 24 pin 600mil DIP CAPHAT
TM
package
houses the M48Z02/12 silicon with a long life lith-
ium button cell to form a highly integrated battery
backed-up memory solution.
The M48Z02/12 button cell has sufficient capacity
and storage life to maintain data and clock function-
ality for an accumulated time period of at least 10
years in the absence of power over the operating
temperature range.
AI01186
11
A0-A10
W
DQ0-DQ7
VCC
M48Z02
M48Z12
G
VSS
8
E
Figure 1. Logic Diagram
A0-A10
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
24
1
PCDIP24 (PC)
Battery CAPHAT
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
40 to 85
C
T
STG
Storage Temperature (V
CC
Off)
40 to 85
C
T
SLD
(2)
Lead Solder Temperature for 10 seconds
260
C
V
IO
Input or Output Voltages
0.3 to 7
V
V
CC
Supply Voltage
0.3 to 7
V
I
O
Output Current
20
mA
P
D
Power Dissipation
1
W
Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260
C for 10 seconds (total thermal budget not to exceed 150
C for longer than 30 seconds).
CAUTION: Negative undershoots below 0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 2. Absolute Maximum Ratings
(1)
Mode
V
CC
E
G
W
DQ0-DQ7
Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
V
IH
X
X
High Z
Standby
Write
V
IL
X
V
IL
D
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
X
X
X
High Z
CMOS Standby
Deselect
V
SO
X
X
X
High Z
Battery Back-up Mode
Notes: X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
Table 3. Operating Modes
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A10
A8
A9
DQ7
W
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
VCC
AI01187
M48Z02
M48Z12
8
1
2
3
4
5
6
7
9
10
11
12
16
15
24
23
22
21
20
19
18
17
14
13
Figure 2. DIP Pin Connections
The M48Z02/12 is a non-volatile pin and function
equivalent to any JEDEC standard 2K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The M48Z02/12 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When V
CC
is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system op-
eration brought on by low V
CC
. As V
CC
falls below
approximately 3V, the control circuitry connects the
battery which maintains data and clock operation
until valid power returns.
DESCRIPTION (cont'd)
2/12
M48Z02, M48Z12
AI01019
5V
OUT
CL = 100pF
CL includes JIG capacitance
1.8k
DEVICE
UNDER
TEST
1k
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
5ns
Input Pulse Voltages
0V to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 4. AC Measurement Conditions
AI01255
LITHIUM
CELL
VPFD
VCC
VSS
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
2K x 8
SRAM ARRAY
A0-A10
DQ0-DQ7
E
W
G
POWER
Figure 3. Block Diagram
READ MODE
The M48Z02/12 is in the Read Mode whenever W
(Write Enable) is high and E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 16,384 locations in the
static storage array. Thus, the unique address
specified by the 11 Address Inputs defines which
one of the 2,048 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
AVQV
) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (t
ELQV
) or Output Enable Access time (t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated
before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (t
AXQX
) but will go indeterminate until the next
Address Access.
3/12
M48Z02, M48Z12
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
(1)
Input Leakage Current
0V
V
IN
V
CC
1
A
I
LO
(1)
Output Leakage Current
0V
V
OUT
V
CC
5
A
I
CC
Supply Current
Outputs open
80
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
3
mA
I
CC2
Supply Current (Standby) CMOS
E = V
CC
0.2V
3
mA
V
IL
(2)
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2.2
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage
I
OH
= 1mA
2.4
V
Notes: 1. Outputs Deselected.
2. Negative spikes of 1V allowed for up to 10ns once per cycle.
Table 6. DC Characteristics
(T
A
= 0 to 70
C or 40 to 85
C; V
CC
= 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
10
pF
C
IO
(2)
Input / Output Capacitance
V
OUT
= 0V
10
pF
Notes: 1. Effective capacitance measured with power supply at 5V.
2. Outputs deselected
Table 5. Capacitance
(1)
(T
A
= 25
C)
Symbol
Parameter
Min
Typ
Max
Unit
V
PFD
Power-fail Deselect Voltage (M48Z02)
4.5
4.6
4.75
V
V
PFD
Power-fail Deselect Voltage (M48Z12)
4.2
4.3
4.5
V
V
SO
Battery Back-up Switchover Voltage
3.0
V
t
DR
Expected Data Retention Time
10
YEARS
Note: 1. All voltages referenced to V
SS
.
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(T
A
= 0 to 70
C or 40 to 85
C)
4/12
M48Z02, M48Z12
Symbol
Parameter
Min
Max
Unit
t
PD
E or W at V
IH
before Power Down
0
s
t
F
(1)
V
PFD
(max) to V
PFD
(min) V
CC
Fall Time
300
s
t
FB
(2)
V
PFD
(min) to V
SO
V
CC
Fall Time
10
s
t
R
V
PFD
(min) to V
PFD
(max) V
CC
Rise Time
0
s
t
RB
V
SO
to V
PFD
(min) V
CC
Rise Time
1
s
t
REC
E or W at V
IH
after Power Up
2
ms
Notes: 1. V
PFD
(max) to V
PFD
(min) fall time of less than t
F
may result in deselection/write protection not occurring until 50
s after
V
CC
passes V
PFD
(min).
2. V
PFD
(min) to V
SO
fall time of less than t
FB
may cause corruption of RAM data.
Table 8. Power Down/Up Mode AC Characteristics
(T
A
= 0 to 70
C or 40 to 85
C)
AI00606
VCC
INPUTS
(PER CONTROL INPUT)
OUTPUTS
DON'T CARE
HIGH-Z
tF
tFB
tR
tREC
tPD
tRB
tDR
VALID
VALID
NOTE
(PER CONTROL INPUT)
RECOGNIZED
RECOGNIZED
VPFD (max)
VPFD (min)
VSO
Figure 5. Power Down/Up Mode AC Waveforms
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E
high as V
CC
rises past V
PFD
(min). Some systems
may perform inadvertent write cycles after V
CC
rises above V
PFD
(min) but before normal system operations begin. Even though a power on
reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
5/12
M48Z02, M48Z12
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