1/17
June 2000
M48Z128
M48Z128Y
1 Mbit (128Kb x8) ZEROPOWER
SRAM
s
INTEGRATED LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
s
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
s
10 YEARS of DATA RETENTION in the
ABSENCE of POWER
s
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
M48Z128: 4.50V
V
PFD
4.75V
M48Z128Y: 4.20V
V
PFD
4.50V
s
BATTERY INTERNALLY ISOLATED UNTIL
POWER IS APPLIED
s
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 128K x 8 SRAMs
s
SURFACE MOUNT CHIP SET PACKAGING
INCLUDES a 28-PIN SOIC and a 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED
SEPARATELY)
s
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY
s
SNAPHAT
HOUSING (BATTERY) IS
REPLACEABLE
Figure 1. Logic Diagram
AI01194
17
A0-A16
W
DQ0-DQ7
VCC
M48Z128
M48Z128Y
G
VSS
8
E
Table 1. Signal Names
A0-A16
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
NC
Not Connected Internally
32
1
TSOP32
(8 x 20mm)
SOH28
Surface Mount Chip Set Solution (CS)
SNAPHAT (SH)
Battery
PMDIP32 (PM)
Module
M48Z128, M48Z128Y
2/17
Figure 2. DIP Connections
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
A15
A11
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A16
NC
VCC
AI01195
M48Z128
M48Z128Y
10
1
2
5
6
7
8
9
11
12
13
14
15
16
30
29
26
25
24
23
22
21
20
19
18
17
A12
A14
W
NC
3
4
28
27
32
31
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260
C for 10 seconds (total thermal budget not to exceed 150
C for longer than 30 seconds).
CAUTION: Negative undershoots below 0.3V are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Note: 1. X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
C
T
STG
Storage Temperature (V
CC
Off)
40 to 70
C
T
BIAS
Temperature Under Bias
10 to 70
C
T
SLD
(2)
Lead Solder Temperature for 10 seconds
260
C
V
IO
Input or Output Voltages
0.3 to 7
V
V
CC
Supply Voltage
0.3 to 7
V
Mode
V
CC
E
G
W
DQ0-DQ7
Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
V
IH
X
X
High Z
Standby
Write
V
IL
X
V
IL
D
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
X
X
X
High Z
CMOS Standby
Deselect
V
SO
X
X
X
High Z
Battery Back-up Mode
DESCRIPTION
The M48Z128/128Y ZEROPOWER
RAM is a
128 Kbit x8 non-volatile static RAM that integrates
power-fail deselect circuitry and battery control
logic on a single die. The monolithic chip is avail-
able in two special packages to provide a highly in-
tegrated battery backed-up memory solution.
The M48Z128/128Y is a non-volatile pin and func-
tion equivalent to any JEDEC standard 128K x8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
write timing or limitations on the number of writes
that can be performed. The 32 pin 600mil DIP
Module houses the M48Z128/128Y silicon with a
long life lithium button cell in a single package.
For surface mount environments ST provides a Chip
Set solution consisting of a 28 pin 330mil SOIC
NVRAM Supervisor (M40Z300) and a 32 pin TSOP
(8 x 20mm) LPSRAM (M68Z128) packages.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery.
3/17
M48Z128, M48Z128Y
Figure 3. Block Diagram
AI01196
INTERNAL
BATTERY
E
VCC
VSS
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
131,072 x 8
SRAM ARRAY
A0-A16
DQ0-DQ7
W
G
POWER
E
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC pack-
age after the completion of the surface mount pro-
cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SNAPHAT battery package is shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form. The part number is "M4Z28-BRxxSH1".
The M48Z128/128Y also has its own Power-fail
Detect circuit. The control circuitry constantly mon-
itors the single 5V supply for an out of tolerance
condition. When V
CC
is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V
CC
. As V
CC
falls
below approximately 3V, the control circuitry con-
nects the battery which maintains data until valid
power returns.
READ MODE
The M48Z128/128Y is in the Read Mode whenev-
er W (Write Enable) is high and E (Chip Enable) is
low. The device architecture allows ripple-through
access of data from eight of 1,048,576 locations in
the static storage array. Thus, the unique address
specified by the 17 Address Inputs defines which
one of the 131,072 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
AVQV
) after the last
address input signal is stable, providing that the E
and G (Output Enable) access times are also sat-
isfied. If the E and G access times are not met, val-
id data will be available after the later of Chip
Enable Access time (t
ELQV
) or Output Enable Ac-
cess Time (t
GLQV
). The state of the eight three-
state Data I/O signals is controlled by E and G. If
the outputs are activated before t
AVQV
, the data
lines will be driven to an indeterminate state until
t
AVQV
. If the Address Inputs are changed while E
and G remain low, output data will remain valid for
Output Data Hold time (t
AXQX
) but will go indeter-
minate until the next Address Access.
M48Z128, M48Z128Y
4/17
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Input Rise and Fall Times
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Figure 4. Hardware Hookup for SMT Chip Set
(1)
Note: 1. For pin connections, see individual data sheets for M40Z300 and M68Z128 at www.st.com.
2. Connect THS pin to V
OUT
if 4.2V
V
PFD
4.5V (M48Z128Y) or connect THS pin to V
SS
if 4.5V
V
PFD
4.75V (M48Z128).
3. SNAPHAT ordered separately.
AI03625
E1CON
VSS
VOUT
THS
(2)
A
M40Z300
E
B
E2CON
E3CON
E4CON
VSS
E2
VCC
M68Z128
E
A0-A16
W
DQ0-DQ7
SNAPHAT
BATTERY
(3)
RST
BL
Figure 5. AC Testing Load Circuit
AI01030
5V
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
1.9k
DEVICE
UNDER
TEST
1k
5/17
M48Z128, M48Z128Y
Table 5. Capacitance
(1, 2)
(T
A
= 25
C, f = 1MHz)
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6. DC Characteristics
(T
A
= 0 to 70
C; V
CC
= 4.75V to 5.5V or 4.5V to 5.5V)
Note: 1. Outputs deselected.
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(T
A
= 0 to 70
C)
Note: 1. All voltages referenced to V
SS
.
2. At 25
C.
Symbol
Parameter
Test Condit ion
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
10
pF
C
IO
(3)
Input / Output Capacitance
V
OUT
= 0V
10
pF
Symbol
Parameter
Test Conditio n
Min
Max
Unit
I
LI
(1)
Input Leakage Current
0V
V
IN
V
CC
1
A
I
LO
(1)
Output Leakage Current
0V
V
OUT
V
CC
1
A
I
CC
Supply Current
E = V
IL
, Outputs open
105
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
7
mA
I
CC2
Supply Current (Standby) CMOS
E
V
CC
0.2V
4
mA
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2.2
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage
I
OH
= 1mA
2.4
V
Symbol
Parameter
Min
Typ
Max
Unit
V
PFD
Power-fail Deselect Voltage
M48Z128
4.5
4.6
4.75
V
M48Z128Y
4.2
4.3
4.5
V
V
SO
Battery Back-up Switchover Voltage
3
V
t
DR
(2)
Data Retention Time
10
YEARS
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