M48Z2M1
M48Z2M1Y
16 Mb (2Mb x 8) ZEROPOWER
SRAM
January 1998
1/12
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
INTEGRATED LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERIES
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
10 YEARS of DATA RETENTION in the
ABSENCE of POWER
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
M48Z2M1: 4.5V
V
PFD
4.75V
M48Z2M1Y: 4.2V
V
PFD
4.50V
BATTERIES ARE INTERNALLY ISOLATED
UNTIL POWER IS APPLIED
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 2Mb x 8 SRAMs
DESCRIPTION
The M48Z2M1/2M1Y ZEROPOWER
RAM is a
non-volatile 16,777,216 bit Static RAM organized
as 2,097,152 words by 8 bits. The device combines
two internal lithium batteries, CMOS SRAMs and a
control circuit in a plastic 36 pin DIP long Module.
The ZEROPOWER RAM replaces industry stand-
ard SRAMs. It provides the nonvolatility of PROMs
without any requirement for special write timing or
limitations on the number of writes that can be
performed.
AI02048
21
A0-A20
W
DQ0-DQ7
VCC
M48Z2M1
M48Z2M1Y
G
VSS
8
E
Figure 1. Logic Diagram
A0-A20
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
36
1
PMLDIP36 (PL)
Module
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
C
T
STG
Storage Temperature (V
CC
Off)
40 to 85
C
T
BIAS
Temperature Under Bias
40 to 85
C
T
SLD
(2)
Lead Soldering Temperature for 10 seconds
260
C
V
IO
Input or Output Voltages
0.3 to 7
V
V
CC
Supply Voltage
0.3 to 7
V
Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260
C for 10 seconds (total thermal budget not to exceed 150
C for longer than 30 seconds).
CAUTION: Negative undershoots below 0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 2. Absolute Maximum Ratings
(1)
Mode
V
CC
E
G
W
DQ0-DQ7
Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
V
IH
X
X
High Z
Standby
Write
V
IL
X
V
IL
D
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
X
X
X
High Z
CMOS Standby
Deselect
V
SO
X
X
X
High Z
Battery Back-up Mode
Notes: X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
Table 3. Operating Modes
VSS
VCC
AI02049
M48Z2M1
M48Z2M1Y
10
1
2
5
6
7
8
9
11
12
13
16
17
18
30
29
26
25
24
23
22
21
20
19
3
4
28
27
32
31
14
15
34
33
36
35
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
A15
A11
G
E
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A16
A18
A12
A14
W
A17
A20
NC
NC
A19
Figure 2. DIP Pin Connections
The M48Z2M1/2M1Y has its own Power-fail Detect
Circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When V
CC
is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system op-
erations brought on by low V
CC
. As V
CC
falls below
approximately 3V, the control circuitry connects the
batteries which sustain data until valid power re-
turns.
READ MODE
The M48Z2M1/2M1Y is in the Read Mode when-
ever W (Write Enable) is high and E (Chip Enable)
is low. The device architecture allows ripple-
through access of data from eight of 16,777,216
locations in the static storage array. Thus, the
unique address specified by the 21 Address Inputs
defines which one of the 2,097,152 bytes of data is
to be accessed. Valid data will be available at the
Data I/O pins within Address Access time (t
AVQV
)
after the last address input signal is stable, provid-
ing that the E (Chip Enable) and G (Output Enable)
access times are also satisfied. If the E and G
access times are not met, valid data will be avail-
DESCRIPTION (cont'd)
Warning: NC = Not Connected.
2/12
M48Z2M1, M48Z2M1Y
able after the later of Chip Enable Access time
(t
ELQV
) or Output Enable Access Time (t
GLQV
). The
state of the eight three-state Data I/O signals is
controlled by E and G. If the outputs are activated
before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
. If the Address In-
puts are changed while E and G remain low, output
data will remain valid for Output Data Hold time
(t
AXQX
) but will go indeterminate until the next Ad-
dress Access.
WRITE MODE
The M48Z2M1/2M1Y is in the Write Mode when-
ever W and E are active. The start of a write is
referenced from the latter occurring falling edge of
W or E. A write is terminated by the earlier rising
edge of W or E.
The addresses must be held valid throughout the
cycle. E or W must return high for minimum of t
EHAX
from E or t
WHAX
from W prior to the initiation of
another read or write cycle. Data-in must be valid
t
DVEH
or t
DVWH
prior to the end of write and remain
valid for t
EHDX
or t
WHDX
afterward. G should be kept
high during write cycles to avoid bus contention;
although, if the output bus has been activated by a
low on E and G, a low on W will disable the outputs
t
WLQZ
after W falls.
AI01030
5V
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
1.9k
DEVICE
UNDER
TEST
1k
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 4. AC Measurement Conditions
AI02050
INTERNAL
BATTERIES
E
VCC
VSS
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
2048K x 8
SRAM ARRAY
A0-A20
DQ0-DQ7
W
G
POWER
E
Figure 3. Block Diagram
3/12
M48Z2M1, M48Z2M1Y
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
40
pF
C
IO
(3)
Input / Output Capacitance
V
OUT
= 0V
40
pF
Notes: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected
Table 5. Capacitance
(1, 2)
(T
A
= 25
C, f = 1 MHz )
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
(1)
Input Leakage Current
0V
V
IN
V
CC
4
A
I
LO
(1)
Output Leakage Current
0V
V
OUT
V
CC
4
A
I
CC
Supply
Current
E = V
IL
, Outputs open
140
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
10
mA
I
CC2
Supply Current (Standby) CMOS
E
V
CC
0.2V
8
mA
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2.2
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage
I
OH
= 1mA
2.4
V
Note: 1. Outputs deselected.
Table 6. DC Characteristics
(T
A
= 0 to 70
C; V
CC
= 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
Parameter
Min
Typ
Max
Unit
V
PFD
Power-fail Deselect Voltage (M48Z2M1)
4.5
4.6
4.75
V
V
PFD
Power-fail Deselect Voltage (M48Z2M1Y)
4.2
4.3
4.5
V
V
SO
Battery Back-up Switchover Voltage
3
V
t
DR
(2)
Data Retention Time
10
YEARS
Notes: 1. All voltages referenced to V
SS
.
2. At 25
C
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(T
A
= 0 to 70
C)
4/12
M48Z2M1, M48Z2M1Y
Symbol
Parameter
Min
Max
Unit
t
F
(1)
V
PFD
(max) to V
PFD
(min) V
CC
Fall Time
300
s
t
FB
(2)
V
PFD
(min) to V
SO
V
CC
Fall Time
10
s
t
WP
Write Protect Time from V
CC
= V
PFD
40
150
s
t
R
V
SO
to V
PFD
(max) V
CC
Rise Time
0
s
t
ER
E Recovery Time
40
120
ms
Notes: 1. V
PFD
(max) to V
PFD
(min) fall time of less than t
F
may result in deselection/write protection not occurring until 200
s after
V
CC
passes V
PFD
(min).
2. V
PFD
(min) to V
SO
fall time of less than t
FB
may cause corruption of RAM data.
Table 8. Power Down/Up Mode AC Characteristics
(T
A
= 0 to 70
C)
AI01031
VCC
E
(PER CONTROL INPUT)
OUTPUTS
DON'T CARE
HIGH-Z
tF
tFB
tR
tWP
tDR
VALID
VALID
(PER CONTROL INPUT)
RECOGNIZED
RECOGNIZED
VPFD (max)
VPFD (min)
VSO
tER
Figure 5. Power Down/Up Mode AC Waveforms
5/12
M48Z2M1, M48Z2M1Y
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