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Электронный компонент: M48Z35AV-10PC1

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1/20
May 2002
M48Z35
M48Z35Y
256 Kbit (32 Kbit x 8) ZEROPOWER
SRAM
FEATURES SUMMARY
s
INTEGRATED, ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, and
BATTERY
s
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
s
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s
WRITE PROTECT VOLTAGES:
(V
PFD
= Power-fail Deselect Voltage)
M48Z35: V
CC
= 4.75 to 5.5V
4.5V
V
PFD
4.75V
M48Z35Y: 4.5 to 5.5V
4.2V
V
PFD
4.5V
s
SELF-CONTAINED BATTERY IN THE
CAPHATTM DIP PACKAGE
s
PACKAGING INCLUDES A 28-LEAD SOIC and
SNAPHAT
TOP (to be Ordered Separately)
s
PIN and FUNCTION COMPATIBLE WITH
JEDEC STANDARD 32K x 8 SRAMs
s
SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP WHICH
CONTAINS THE BATTERY and CRYSTAL
Figure 1. 28-pin CAPHATTM DIP Package
Figure 2. 28-pin SOIC Package
PCDIP28 (PC)
Battery CAPHAT
28
1
SNAPHAT (SH)
Crystal / Battery
SOH28 (MH)
28
1
M48Z35, M48Z35Y
2/20
TABLE OF CONTENTS
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic Diagram (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
DIP Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SOIC Connections (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AC Measurement Load Circuit (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operating Modes (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
READ Mode AC Waveforms (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
READ Mode AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WRITE Enable Controlled, WRITE AC Waveforms (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable Controlled, WRITE AC Waveforms (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WRITE Mode AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power Down/Up Mode AC Waveforms (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power Down/Up AC Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power Down/Up Trip Points DC Characteristics (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
V
CC
Noise And Negative Going Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Supply Voltage Protection (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SNAPHAT Battery Table (Table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/20
M48Z35, M48Z35Y
DESCRIPTION
The M48Z35/Y ZEROPOWER
RAM is a 32 Kbit
x 8, non-volatile static RAM that integrates power-
fail deselect circuitry and battery control logic on a
single die. The monolithic chip is available in two
special packages to provide a highly integrated
battery backed-up memory solution.
The M48Z35/Y is a non-volatile pin and function
equivalent to any JEDEC standard 32K x8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed. The 28 pin 600mil
DIP CAPHATTM houses the M48Z35/Y silicon with
a long life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery. The unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery
damage due to the high temperatures required for
device surface-mounting. The SNAPHAT housing
is keyed to prevent reverse insertion.
The SOIC and battery packages are shipped sep-
arately in plastic anti-static tubes or in Tape & Reel
form.
For the 28 lead SOIC, the battery package (i.e.
SNAPHAT) part number is "M4Z28-BR00SH1."
Figure 3. Logic Diagram
Table 1. Signal Names
AI01616D
15
A0-A14
W
DQ0-DQ7
VCC
M48Z35
M48Z35Y
G
VSS
8
E
A0-A14
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable Input
G
Output Enable Input
W
WRITE Enable Input
V
CC
Supply Voltage
V
SS
Ground
M48Z35, M48Z35Y
4/20
Figure 4. DIP Connections
Figure 5. SOIC Connections
Figure 6. Block Diagram
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
W
A11
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A12
A14
VCC
AI01617D
M48Z35
M48Z35Y
8
1
2
3
4
5
6
7
9
10
11
12
13
14
16
15
28
27
26
25
24
23
22
21
20
19
18
17
AI02303C
8
2
3
4
5
6
7
9
10
11
12
13
14
22
21
20
19
18
17
16
15
28
27
26
25
24
23
1
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
W
A11
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A12
A14
VCC
M48Z35Y
AI01619B
LITHIUM
CELL
VPFD
VCC
VSS
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
32K x 8
SRAM ARRAY
A0-A14
DQ0-DQ7
E
W
G
POWER
5/20
M48Z35, M48Z35Y
MAXIMUM RATING
Stressing the device above the rating listed in the
"Absolute Maximum Ratings" table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Note: 1. For DIP package: Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer
than 30 seconds).
2. For SO package: Reflow at peak temperature of 215C to 225C for < 60 seconds (total thermal budget not to exceed 180C for
between 90 to 120 seconds).
CAUTION: Negative undershoots below 0.3V are not allowed on any pin while in the Battery Back-up mode.
Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
Grade 1
0 to 70
C
Grade 6
40 to 85
C
T
STG
Storage Temperature (V
CC
Off, Oscillator Off)
SNAPHAT
40 to 85
C
SOIC
55 to 125
C
T
SLD
(1,2)
Lead Solder Temperature for 10 seconds
260
C
V
IO
Input or Output Voltages
0.3 to 7.0
V
V
CC
Supply Voltage
0.3 to 7.0
V
I
O
Output Current
20
mA
P
D
Power Dissipation
1
W