1/18
August 1999
M48Z35
M48Z35Y
256 Kbit (32Kb x8) ZEROPOWER
SRAM
s
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
s
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
s
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
M48Z35: 4.50V
V
PFD
4.75V
M48Z35Y: 4.20V
V
PFD
4.50V
s
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
s
PACKAGING INCLUDES a 28-LEAD SOIC and
SNAPHAT
TOP (to be Ordered Separately)
s
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
s
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 32K x8 SRAMs
DESCRIPTION
The M48Z35/35Y ZEROPOWER
RAM is a 32
Kbit x8 non-volatile static RAM that integrates
power-fail deselect circuitry and battery control
logic on a single die. The monolithic chip is avail-
able in two special packages to provide a highly in-
tegrated battery backed-up memory solution.
Figure 1. Logic Diagram
AI01616D
15
A0-A14
W
DQ0-DQ7
VCC
M48Z35
M48Z35Y
G
VSS
8
E
Table 1. Signal Names
A0-A14
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
28
1
28
1
SOH28 (MH)
SNAPHAT (SH)
Battery
PCDIP28 (PC)
Battery CAPHAT
M48Z35, M48Z35Y
2/18
Figure 2A. DIP Pin Connections
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
W
A11
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A12
A14
VCC
AI01617D
M48Z35
M48Z35Y
8
1
2
3
4
5
6
7
9
10
11
12
13
14
16
15
28
27
26
25
24
23
22
21
20
19
18
17
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below 0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
Grade 1
Grade 6
0 to 70
40 to 85
C
T
STG
Storage Temperature (V
CC
Off)
SNAPHAT
SOIC
40 to 85
55 to 125
C
T
SLD
(2)
Lead Solder Temperature for 10 seconds
260
C
V
IO
Input or Output Voltages
0.3 to 7
V
V
CC
Supply Voltage
0.3 to 7
V
I
O
Output Current
20
mA
P
D
Power Dissipation
1
W
Figure 2B. SOIC Pin Connections
AI02303C
8
2
3
4
5
6
7
9
10
11
12
13
14
22
21
20
19
18
17
16
15
28
27
26
25
24
23
1
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
W
A11
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A12
A14
VCC
M48Z35Y
3/18
M48Z35, M48Z35Y
The M48Z35/35Y is a non-volatile pin and function
equivalent to any JEDEC standard 32K x8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed. The 28 pin 600mil DIP
CAPHATTM houses the M48Z35/35Y silicon with a
long life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery. The unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery
damage due to the high temperatures required for
device surface-mounting. The SNAPHAT housing
is keyed to prevent reverse insertion.
Table 3. Operating Modes
(1)
Note: 1. X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
2. See Table 7 for details.
Mode
V
CC
E
G
W
DQ0-DQ7
Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
V
IH
X
X
High Z
Standby
Write
V
IL
X
V
IL
D
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
(2)
X
X
X
High Z
CMOS Standby
Deselect
V
SO
X
X
X
High Z
Battery Back-up Mode
Figure 3. Block Diagram
AI01619B
LITHIUM
CELL
VPFD
VCC
VSS
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
32K x 8
SRAM ARRAY
A0-A14
DQ0-DQ7
E
W
G
POWER
M48Z35, M48Z35Y
4/18
The SOIC and battery packages are shipped sep-
arately in plastic anti-static tubes or in Tape & Reel
form.
For the 28 lead SOIC, the battery package (i.e.
SNAPHAT) part number is "M4Z28-BR00SH1".
The M48Z35/35Y also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
tors the single 5V supply for an out of tolerance
condition. When V
CC
is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V
CC
. As V
CC
falls
below approximately 3V, the control circuitry con-
nects the battery which maintains data until valid
power returns.
READ MODE
The M48Z35/35Y is in the Read Mode whenever
W (Write Enable) is high, E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 264,144 locations in the
static storage array. Thus, the unique address
specified by the 15 Address Inputs defines which
one of the 32,768 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
AVQV
) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (t
ELQV
) or Output Enable Access time
(t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (t
AXQX
) but will go indeterminate until the next
Address Access.
WRITE MODE
The M48Z35/35Y is in the Write Mode whenever
W and E are low. The start of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
of t
EHAX
from Chip Enable or t
WHAX
from Write En-
able prior to the initiation of another read or write
cycle. Data-in must be valid t
DVWH
prior to the end
of write and remain valid for t
WHDX
afterward. G
should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G, a low on W
will disable the outputs t
WLQZ
after W falls.
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Input Rise and Fall Times
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Figure 4. AC Testing Load Circuit
AI03211
CL = 100pF or
5pF
CL includes JIG capacitance
645
DEVICE
UNDER
TEST
1.75V
5/18
M48Z35, M48Z35Y
Table 5. Capacitance
(1, 2)
(T
A
= 25 C)
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6. DC Characteristics
(T
A
= 0 to 70 C or 40 to 85 C; V
CC
= 4.75V to 5.5V or 4.5V to 5.5V)
Note: 1. Outputs deselected.
2. Negative spikes of 1V allowed for up to 10ns once per cycle.
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(T
A
= 0 to 70 C or 40 to 85 C)
Note: 1. All voltages referenced to V
SS
.
2. At 25 C.
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
10
pF
C
IO
(3)
Input / Output Capacitance
V
OUT
= 0V
10
pF
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
(1)
Input Leakage Current
0V
V
IN
V
CC
1
A
I
LO
(1)
Output Leakage Current
0V
V
OUT
V
CC
5
A
I
CC
Supply Current
Outputs open
50
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
3
mA
I
CC2
Supply Current (Standby) CMOS
E = V
CC
0.2V
3
mA
V
IL
(2)
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2.2
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage
I
OH
= 1mA
2.4
V
Symbol
Parameter
Min
Typ
Max
Unit
V
PFD
Power-fail Deselect Voltage (M48Z35)
4.5
4.6
4.75
V
V
PFD
Power-fail Deselect Voltage (M48Z35Y)
4.2
4.35
4.5
V
V
SO
Battery Back-up Switchover Voltage (M48Z35/35Y)
3.0
V
t
DR
(2)
Expected Data Retention Time
10
YEARS
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